Silicon carbide high-power devices

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 10, OCTOBER 1996

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ilicon Carbide High-Power Devices Charles E. Weitzel, Senior Member, IEEE, John W . Palmour, Member, IEEE, Calvin H. Carter, Jr., Karen Moore, Member, IEEE, Kevin J. Nordquist, Scott Allen, Christine Thero, Member, IEEE, and Mohit Bhatnagar

r

Abstruct- In recent years, silicon carbide has received increased attention because of its potential for high-power devices. The unique material properties of Sic, high electric breakdown field, high saturated electron drift velocity, and high thermal conductivity are what give this material its tremendous potential in the power device arena. 4H-Sic Schottky barrier diodes (1400 V) with forward current densities over 700 A/cm2 at 2 V have been demonstrated. Packaged SIT’S have produced 57 W of output power at 500 MMz. S i c UMOSFET’s (1200 V) are projected to have 15 times the current density of Si IGBT’s (1200 V). Submicron gate length 4H-Sic MESFET’s have achieved fmax = 32 GHz, f~ = 14.0 GHz, and power density = 2.8 W/mm @ 1.8 GHz. The performance of a wide variety of S i c devices will be compared to that of similar Si and GaAs devices and to theoretically expected results.

High Resistivity Schottky Contact

Epitaxial Drift Layer (t = 10 p) Nd 1 X ii:

Cm-’

Substrate (t = 11 mils)

Ohmic Contact Fig 1 Cross sectional view of a Sic Schottky diode with high-resistivity edge termination

I. INTRODUCTION

I

N recent years, silicon carbide has received increased

attention because of its potential for a wide variety of highpower devices [ 11-[3]. The unique material properties of Sic, high electric breakdown field of 4 x lo6 V/cm, high saturated electron drift velocity of 2 x l o 7 cm/s, and high thermal conductivity of 4.9 Wkm-”K are what give this material its tremendous potential in the power device arena. The data in Table I allows a comparison of the basic material properties of silicon, gallium arsenide, and silicon carbide. The two S i c polytypes that are having the biggest impact on power devices, 6H and 4H, are both listed in Table I. The most significant difference between 6H and 4H is that the electron mobility in 4H-Sic is two times that of 6H-SIC perpendicular to the e-axis and almost 10 times that of 6H-SIC parallel to the caxis [4]. This fact alone explains the increased importance of 4H-Sic. S i c devices will have better performance compared to Si and GaAs devices for high voltage applications because of Sic’s higher breakdown field, saturated drift velocity, and thermal conductivity even though the electron mobility is lower. Some insight into how these material parameters affect device performance can be seen by studying the various device figures of merit that have been proposed over the last 30 years CS1-[91.

Manuscript received October 31, 1995, revised April 30, 1996 This work was supported in part by the Office of Naval Research, Department of the Air Force, Wright Laboratones, and, NASA Lewis Research Center C E Weitzel, K Moore, K J Nordquist, C Thero, and M Bhatnagar are with the Phoenix Coiporate Research Laboratories, Motorola, Inc , Tempe, AZ 85284 USA J. W Palmour, C. H Carter, Jr., and S Allen are with Cree Research, Durham, NC 27713 USA Publisher Item Identifier S 00 18-9383(96)07217-6

In this paper, a wide variety of S i c power devices-Schottky and p-n junction diodes, thyristors, UMOSFET’s, SIT’S, RF MESFET’s, and RF JFET’s-will be discussed in terms of fabrication, simulated performance, and state-of-the-art experimental performance. Where possible, the simulated and experimental results will be compared with those of comparable Si and GaAs devices. 11.

SCHOTTKY AND

p-n JUNCTIONDIODES

The least complex S i c power device is the Schottky rectifier (Fig. l), which consists of an N+ doped substrate (thickness % 11 mil) with backside ohmic contact, a lightly doped (1 x 10l6~ m - ~epitaxial ) drift layer (thickness M 10 um), and a topside Schottky contact with a high-resistivity edge termination. The Schottky diode is fabricated by evaporating a high work function metal, such as titanium, nickel, or gold, onto the epitaxial layer to form the Schottky contact and by depositing an ohmic contact metal onto the back of the N+ substrate [lo]. The order of these depositions may be reversed to accommodate annealing of the ohmic contact. The high resistivity edge termination is achieved by implanting an inert species, such as argon, which damages the exposed semiconductor causing a high resistivity region. The process is self-aligned to the Schottky contact because the Schottky metal acts as a mask preventing damage under the contact [ 111. The most important device properties are high reverse breakdown voltage and low forward resistance which, in tum, produces a high forward current density. By calculating the specific Ron of Si, GaAs, and 4H-SiC Schottky diodes at various breakdown voltages, the lower resistance of 4H-Sic

0018-9383/96$05 .OO 0 1996 IEEE

WEITZEL et al.: SILICON CARBIDE HIGH-POWER DEVICES

MATERIAL PROPERTIES

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OF SILICON,

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TABLE I GALLIUM ARSENIDE, AND SILICON

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4H-SICi

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.: GaAs 4H-Sic Experimental H0,0,0 0 Data

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Analytical Results :Si GaAs 4H-Sic-

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Schottky diodes at high voltages can be easily quantified. The Schottky diode specific R o n is the sum of the epitaxial drift layer and the N+ substrate resistances both of which are calculated using (1) where is layer thickness, Nd is layer doping, and pUnis electron mobility [12].

w

Ron,sp =

w/(qNdh).

(1)

The drift layer doping density determines the breakdown voltage and drift layer thickness is chosen so that depletion layer punch-through occurs at the same voltage as the avalanche breakdown. For these calculations, the substrate is assumed to be 5 mil thick and doped 1 x 1020cm-3. The substrate ohmic contact resistance is assumed to be zero for all three materials. Using readily available [4], [13], [14] doping dependent material parameters, the analytical results (solid and dashed lines) are shown in Fig. 2 where specific Ron for Si, GaAs, and 4H-Sic is plotted versus breakdown voltage. At low-breakdown-voltages, the specific Ron for each material is dominated by the specific substrate resistance. For higher breakdown voltages, the drift layer must be thicker and have a lower doping density both of which increase the specific Ron.At low voltages, GaAs Schottky diodes have the lowest specific Ron,but at sufficiently high voltage 2200 V the higher

0

breakdown field of 4H-Sic becomes the dominant parameter and the 4H-SiC Schottky has the lowest specific Ron. These analytical results show that the specific Ron of a 1000 V 4HS i c Schottky is 15 times lower than that of a 1000 V GaAs Schottky and over 200 times lower than that of a 1000 V Si Schottky. Experimental results for GaAs and 4H-Sic Schottky diodes are included to help validate the modeled results. GaAs diodes (open and solid squares) with 200 V and 610 V breakdown voltages have 682 A/cm2 and 500 A/cm2 forward current densities at 2 V, and 1.43 mO-cm2 and 2.04 mRcm2 specific Ron's, respectively [15], [16] The specific Ron's were measured at large forward voltages (1.5-2.5 V) where the forward current density saturates and series resistance limits conduction. The 200 V GaAs diode is a Schottky diode and the 610 V GaAs diode is a merged p-i-n Schottky (MPS) which includes a p-i-n diode in parallel with the Schottky diode [16], [ 171. Forward biasing2 p-i-n diode causes minority carrier injection which significantly reduces the specific R,,, and therefore the specific Ron for the GaAs MPS diode is below the modeled Schottky diode curve. The forward and reverse I-V curves for a 4H-Sic Schottky diode (solid ellipse)

IEEE TRANSACTIONS ON ELECTRON DEVICE$, VOL. 43, NO. 10, OCTOBER 1996

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Anode! Ohmic Contacts

1 A = 3 . 2 1 ~ 1 0 -cm2 ~ 1.5

3 I

N-type

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I

I

-0.5

P' Epitaxy

-1.0

-1.5 -2.0

Cathode Ohmic Contact

4H-Sic npnp Thyristor

L

-25

Fig. 4. Cross sectional view of mesa isolated, n-p-n-p S i c thyristor.

-1000 -800 -600 -400 -200

are plotted in Fig. 3. This diode has 732 A/cm2 forward current density at 2 V, 1.5 mR-cm2 specific Ron,and 1400 V breakdown voltage which were achieved with a 10-pm-thick epitaxial drift layer doped 7.5 x lOI5 cmP3 and argon implant damage termination [ l l ] . The argon implant dose was 1 x cm-' at an energy of 30 keV. This particular diode has higher than desired reverse leakage current. Recently, other workers have reported 4H-Sic Schottky diodes (solid and open circles) with 2 m0-cm2 and 1.4 mR-cm2 specific Ron and 1000 V and 800 V breakdown voltages, respectively [18], [19]. A somewhat more complex device is the p-i-n diode which substitutes a P+ epitaxial layer and a p-type ohmic contact for the Schottky contact. A 21000 V p-n diode which incorporates a mesa edge termination lhas been demonstrated with 6H-Sic [20]. An RIE defined 6H-Sic mesa p-i-n diode with a 4.5 kV blocking voltage has also1 been demonstrated using a 45 pm ~ m - ~and) a 1.5 pm thick P+ thick N- drift layer (1 x contact layer [21].

0

200 400 600 800 1000

CATHODE VOLTAGE (V) Fig. 5 Forward and reverse bias I-V characteristics of a 600 V 4H-Sic n-p-n-p thyristor at 27 OC The area is 3 . 2 x cm2 I f = 1 8 A at 37

v

no gate current. The voltage drop for a current of -1 A (1000 A/cm') was -4.0 V. The low on-resistance of the 4H devices resulted in a lower voltage drop for a current density of 500-1000 A/cm2 than for 6H devices, despite the higher built-in potential of 2.85 V for 4H as compared with 2.6 V for 6H. High-temperature measurements on these earlier 4H thyristors confirmed their capability to successfully operate at 500 "C with a cathode voltage of -200 V. At 500 "C, the forward breakover voltage with no gate current was still above -200 V and the leakage current at -160 V was only 5 pA (4.8 x A/cm2). This yields a high "on-off' current ratio of lo5 at 500 "C which is adeptable for a power switch. More recently, n-p-n-p 4H-Sic thyristors have achieved blocking voltages of 600 V in both forward and reverse bias, as shown in Fig. 5. The forward characteristic for this thyristor 111. THYRISTORS is in the third quadrant because the gate electrode is made For very high-voltage l(5 kV-10 kV) applications, such as to n-type material and the P- epitaxial layer supports the traction control and high-voltage DC transmission, Si bipolar reverse breakdown voltage. The forward breakover voltage devices have much lower on-resistances than unipolar devices, could be reduced to less than 30 V with a gate current of such as MOSFET's. The same is expected to be true for S i c -2.5 mA (0.77 A/cm2). After the forward current snaps back bipolar devices. At these very high voltages a single S i c at a holding current of 2.3 mA, the device has a rated forward thyristor could replace a stack of several Si thyristors and current of 1.8 A (563 A/cm2) with a voltage drop of 3.7 V. The thereby achieve a lower forward voltage drop. In addition it cathode leakage current at a forward bias of -500 V was only is expected that properly designed S i c bipolar devices, which 3.7 nA at 27 "C, yielding an on-off ratio of 5 x lo8. A larger take advantage of the high-breakdown electric field of Sic, area thyristor (1.61 x lo-' cm2) had a 10 A rated on-current will have lower voltage drops than corresponding Si bipolar and blocked 200 V in both directions. Initial measurements of devices. This is expected to be the case in spite of the higher lower voltage thyristors indicate that 4H-SIC thyristors have built-in voltage for S i c junctions. The most promising S i c turn-off times ranging from 360 ns to 640 ns. Fast turn-off thyristor structure to date has been an n-p-n-p de;ice (Fig. 4) in times indicate that these devices can operate at much higher 4H-SiC, the design of which has been reported previously [22], (> 150 kHz) than typical silicon thyristors [23]. frequencies because it allows the use of a low-resistivity n-type substrate. The mesa structure was utilized with all the doping being done IV. UMOSFET'S in situ during epitaxial growth [23]. The device periphery was terminated using a reactive ion etched mesa. Early 4H The S i c UMOSFET (Fig. 6) has a backside drain ohmic devices showed a forward blockiiig voltage of -375 V with contact, N+ doped substrate (thickness NN 11 mil), and epitaxial

WEITZEL et al.: SILICON CARBlDE HIGH-POWER DEVICES

Source Ohmic Contact

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Oxide

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R E

4H, Ma‘del

1000

3

4H-Sic UMOSFET (260V) Experimental

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100 Experimental

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Drain Ohmic Contact Fig. 6. Cross section of a S i c UMOSFET. Source to drain current flows in inversion layers formed at the p-type layer-oxide interfaces.

a

10

1

0

-

drift layer similar to that of the Schottky diode. The upper portion of the UMOSFET contains an epitaxial p-type layer, ion implanted N+ source contact regions, and a source ohmic contact. The upper portion of the UMOSFET is enclosed by trenches which contain metal or polysilicon gate electrodes which are spaced from the p-type layer and n-type drift region by the gate oxide Si02 [22], [24]. The device fabrication starts . with an N+ S i c substrate on which is grown in succession the n-type drift layer and the p-type layer. The N+ source contact regions are typically implanted at an elevated temperature and activated at an even higher temperature [25]. RIE is used to - / form the trenches on either side of the p-type layer [26],[27]. After the gate oxide (Si02) is grown and annealed [28], ohmic contacts are formed on the source and drain areas [29]. Finally the gate metal and interconnect metal is defined. During device operation current flows from the N+ source contacts through an inversion layer (minority carriers) at both vertical surfaces of the p-type layer across the n-type drift layer (majority carriers) to the N+ substrate. The current flow from source to drain is controlled by the potential on the gate electrode. The higher forward current density of an ideal 1200 V 4H-SIC UMOSFET compared to those of a 1200 V vertical silicon MOSFET and a 1200 V Si IGBT is shown by the analytical and experimental results in Fig. 7. The Si and 4HS i c MOSFET’s analytical results (solid lines) were calculated based on a design approach that minimizes R,, for a given breakdown voltage [30]. Inversion layer electron mob 1000 cm2/V-s and 20 cm2/V-s were assumed for the Si and 4H-Sic UMOSFET’s, respectively. In spite of the extremely low 4H-SIC inversion layer mobility, the ideal current density of the 4H-Sic UMOSFET is 100 timeshigher than that of a Si MOSFET primarily because of the much lower specific R,, of the 4H-Sic drift layer. An experimental data point for a typical 1200 V, 10 A Si IGBT is also included in Fig. 7 for comparison. This device has a 2.5 V forward voltage drop at an operating current density of 75 A/cm2 [31]. The analytically expected current density of the ideal 4H-Sic UMOSFET is 15 times higher than that of a present day, state-of-the-art typical Si IGBT. At present S i c UMOSFET’s are in an early stage of development and must be impro.4 significantly to reach the potential illustrated by the ia+I analytical data shown

1

0.5

1.5 2 2.5 3 Forward Voltage (V)

4

3.5

Fig. 7. Current density versus forward voltage of ideal 1200 V Si and 1200 V 4H-Sic UMOSFET’s (modeled), a typical 1200 V Si IGBT (experimental), and a 260 V 4H-Sic UMOSFET (experimental).

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I

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T=300K 1.6

1.2

0.8

0.4

0

0

2.0

4.0

6.0

8.0

10

DRAIN VOLTAGE (V) Fig. 8. I-V curves of a large area (0.01 cm’), 2 A 4H-Sic vertical UMOS power FET showing the low-voltage, high-current characteristics. Specific R,, = 13.2mQ-cm’.

in Fig. 7. Experimentally, the first vertical UMOS power FET’s in 4H-Sic were capable of blocking 150 V and had a current rating of 67 mA (100 A/cm2) at V d = 3.3 V which corresponds to a specific R,, of 33 mR-cm2 [14]. cm2) and The I-V characteristic of the largest (1 x highest current 4H-Sic UMOSFET achieved to date is shown in Fig. 8. This device has a blocking voltage of 175 V, a drain current of 2 A (200 A/cm2) at v d = 2.65 V, a transconductance of 454 mS (5.3 mS/mm), and a specific R,, of 13.2 mR-cm2 at a gate bias of f20 V. On the other hand, the highest voltage 4H-Sic UMOSFET has a 260 V blocking voltage, a current rating of 100 mA (100 A/cm2) at V d = 1.8 V, and a specific R,, of 18 mR-cm2 [23].

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 10, OCTOBER 1996

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Ohmic

Source Ohmic Contact

Schottky

\

P-Buffer N-type Substrate Fig 10 Cross section of an RF SIC MESFET Current flows laterally from source to drain confined to the n-type channel by the P- buffer layer and controlled by the Schottky gate electrode.

-

Drain Ohmic Contact Fig 9 Cross sectional view of a S i c static induction transistor (SIT) Current flows vertically from source to drain subject to Schottky gate control.

Experimental data from the highest blocking voltage (260 V) 4H-Sic UMOSFET is also included in Fig. 7. The current density of the 260 V 4H-Sic UMOSFET is approximately one order of magnitude below that of the ideal 1200 V 4HS i c UMOSFET. The lower than expected current density of the present 4H-Sic UMOSFET’s is most likely a result of its very low inversion channel mobility (7-12 cm2/V-s) [32]. Higher inversion channel mobilities are expected from improvements in S i c oxidation technology. It is expected that with improvements in SIC material quality, fabrication processes, and device design additional increases in breakdown voltage will be realized. The reader is cautioned not to draw any conclusions about the relative merits of the 260 V S i c UMOSFET and the 1200 V Si devices because these devices have significantly different breakdown voltages. The 4H-Sic experimental data is plotted in Fig. 7 to show the, as yet, unrealized potential of 4H-Sic UMOSFET’s. V. SIT’s (STATICINDUCTION TRANSISTORS)

-

The cross section (Fig. 9) of a S i c SIT bears a resemblance to that of the UMOSFET (Fig. 6), but the details of its structure and method of operation are significantly different. Like all of the previously discussed devices, the SIT is a vertical device with an ohmic source contact on the top and an ohmic drain contact on the back of the wafer. Between these two N+ regions is an N- epitaxial drift layer whose doping is one of the factors that determines the device breakdown voltage and pinch-off voltage. Trenches are etched to define the channel region and Schottky gate contacts are formed in the bottom and along the sidewalls of the trench. Majority carriers flow from the source contact to the drain contact through an accumulation layer in the n-type channel region. By applying a negative voltage to the gate contact the current flow can be modulated and even decreased to zero when depletion regions under each gate contact meet in the middle of the channel. In DC operation the drain current does not saturate, but resembles that of a vacuum triode [33]. 6H-Sic SIT’s have achieved a blocking voltage of 120 V, a channel current of 350 mA/cm, and a transconductance of 4.0 mS/mm. A single 1 cm periphery 6H device delivered 0.35 W/mm power density and 10 combined chips delivered 38 W pulsed power at 175 MHz [34]. Using

0.5 pm lithography, 4H-Sic SIT’s achieved a current density of 100 mA/mm of source periphery, a voltage gain of 15, a transconductance of 7.5 mS/mm, a blocking voltage of 200 V, and a cut-off frequency fmax of 4 GHz. Packaged transistors (4.75 cm periphery) delivered 57 W pulsed output power with 43% power added efficiency at 12 dB gain at 500 MHz [35]. Packaged transistors with combined 16.5 cm periphery delivered 225 W output power with an associated gain of 8.7 dB at 600 MHz [36]. This power density (1.36 W/mm) at 600 MHz is significantly higher than the 0.76 W/mm at 225 MHz and 0.52 W/mm at 900 MHz achieved with Si SIT’s [37]. VI. RF MESFET’s Unlike the preceding devices, S i c RF FET’s are lateral devices with both source and drain contacts on the top surface of the wafer (Fig. 10). Source and drain ohmic mntacts are typically placed on top of an N+ epitaxial-layer and are separated by a more lightly doped (1 x n-type channel region. The majority carriers flow in the channel from source to drain and are controlled by a Schottky gate contact. Typically device isolation was achieved with a Pbuffer layer on a conducting substrate. More recently h&resistivity substrates have been used in place of the P- buffer layer to achieve higher cut-off frequency devices 7381. The superior power density capability of 4H-Sic RF MESFET’s is demonstrated by the analytical and experimental results shown in Fig. 11 [39]. The device parameters which were important in differentiating the power density of the Si, GaAs, and 4HS i c MESFET’s were low field electron mobility, breakdown field, and electron saturation velocity. At a doping density of 1x 1017cm-3 the electron mobility of 4H-Sic is 560 cm2/V-s which is slightly lower than that of Si (800 cm2/V-s) and significantly lower than that of GaAs (4900 cm2/V-s). On the other hand, the breakdown field of 4H-Sic is 10 times that of Si and GaAs, and the saturated drift velocity is 2 times that of Si and GaAs. The experimental data give added credibility to the analytical results. Si LDMOS data was substituted because of the unavailability of Si MESFET data [39]. At low voltages, GaAs MESFET’s, which have higher electron mobility, have the highest power density [40]. The higher power density of S i c MESFET’s is only achieved at drain voltages higher than those normally used with either Si or GaAs devices. It is

WEITZEL et al.: SILICON CARBIDE HIGH-POWER DEVICES

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Fig. 11. RF power density

data points.

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40

.

,35 - - a -30

35

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2

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2P

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20

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IH211

g.

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15 10 5

-5 0

-15

-10

-5

5 Pin (dBm) O

10

15

0 20

Fig 12 Output power, power gain, and power added efficiency versus input power of a packaged 4H-SIC MESFET te5ted at 850 MHz MESFET was tuned for maximum output power

worth noting that the experimental results of the more mature technologies, Si and GaAs, lie much closer to their analytical curves than do the 4H-Sic experimental results. Lower contact and channel resistances will move experimental SIC results closer to the analytical curve and thereby to higher power densities. In addition, realizing breakdown voltages closer to theoretical limits for a given doping density will extend the experimental data points to higher drain voltages and also to higher power densities. The output power of 4H-Sic MESFET’s has been measured both on-wafer and in ceramic packages using a loadpull system. The highest power density for 4H-Sic MESFET’s measured on-wafer is 2.8 W/mm with a power added efficiency

0.1

I

10

Frequency (GHz)

Fig. 13. IH211 and MSG/MAG versus frequency for a 4H-Sic MESFET fabricated on a high-resistivity Sic substrate. f t = 16.2 GHz. fr,,, = 32 GHz.

of 12.7% at 1.8 GHz with a channel doping of 1 . 7 ~ cmP3 and a drain voltage of 54 V [41]. For class A operation the power density of packaged 4H-Sic MESFET’s was 3.1 W/mm for v d s = 50 V with a power added efficiency of 38.9% and a small signal power gain of 20 dB at 850 MHz (Fig. 12) [42]. Biasing the same device for class B operation yielded a power density of 2.3 W/mm with a power added efficiency of 65.7% with v d s = 40 V. A larger (2 mm) 6H-Sic MESFET delivered 3.5 W with 45.5% power added efficiency at 6 GHz operating with a drain bias of 40 V [43]. Recently the use of highresistivity substrates has substantially increased the frequency performance of S i c MESFET’s [44].Sub-micron gate length 4H-Sic MESFET’s fabricated using conducting and highresistivity substrates have achieved frIlax = 16.3 GHz and 32

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL 43, NO 10, OCTOBER 1996

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I

Ohmic

I

,Metal 25 h

20