International Journal of Physical, Chemical & Mathematical Sciences, Vol. 2; No. 2: ISSN: 2278-683X (July-Dec. 2013)
Silicon-on-Insulator – Future Transistor Technology Rajiv Sharma Associate Prof., Deptt. of ECE, Vaish College of Engineering, Rohtak (Haryana) Email:
[email protected]
Abstract: The International Technology Roadmap for Semiconductors recommends not only switching from bulk to silicon-on-insulator (SOI), but also evolving from single-gate planar SOI transistors to multiple-gate devices with improved current drive and short-channel characteristics. As the bulk silicon CMOS processes are reaching their limit in terms of device miniaturization and fabrication, SOI technology gives a good alternative to that. SOI technology is considered to take the CMOS processing to its ultimate scalability. A brief review of work published by many research groups is presented in this paper. Firstly, different types of SOI MOSFET are discussed briefly and then multiple gate MOSFETs are discussed, and their pros and cons over bulk CMOS technology are explained.
Keywords: MOSFETs, CMOS, Silicon-on-Insulator, ITRS, FD SOI MOSFET, PD SOI MOSFET Accepted On: 11.12. 2013
1. Introduction CMOS integrated circuits are almost exclusively fabricated on bulk silicon substrates for two reasons: the supply of silicon wafers in abundance and because the good oxide can be readily grown on silicon, which is not possible on germanium or on some other semiconductors [1]. Scaling CMOS devices increases functionality per cost and the improvement in the performance of devices. As the scaling continues, it becomes harder to fabricate devices without compromising performance due to undesirable effects such as threshold voltage roll- off, drain induced barrier lowering (DIBL) and degraded sub threshold slope [2, 3]. Beside the short channel effects, a number of technological barriers exist. As the gate length is reduced the wavelength of the light for the lithography equipment needs to reduce. Manufacturing such optical equipment at smaller wavelength becomes harder due to the availability of materials that should be used for these wavelengths [4]. Further with gate length reduction, gate oxide thickness must also be reduced, resulting in an increase in quantum mechanical tunneling in excessively high electric fields. Eventually silicon oxide must be replaced with a high-k material so the physical thickness of the material can be increased. As the device length is reduced the high doping is required in between the source and drain which in turns increases the parasitic capacitance between diffused source, drain and substrate. Considering these facts for a long time search for the breakthrough technology has been undergoing. SOI structures consist of a film of single crystalline Si separated by a layer of SiO2 from the bulk substrate [5]. Silicon-on-insulator (SOI) technology gives many advantages over bulk silicon CMOS processing. In particular higher speed, lower power dissipation, high radiation tolerance, lower parasitic capacitance, low short channel effects, high sub threshold voltage swing, manufacturing compatibility with the existing bulk silicon CMOS technology. In this paper some of the SOI CMOS models which are currently considered as an alternative to bulk CMOS technology and related concepts are presented.
2. Motivation SOI chips consist of millions of single-transistor islands dielectrically isolated from each other and from the underlying silicon substrate. On one hand, the vertical isolation protects the thin active silicon layer from most parasitic effects induced by the very bulky substrate, leakage currents, radiation-induced photocurrents and latch-up effects etc. On the other hand, the lateral isolation makes inter device separation in SOI free of complicated schemes of trench or well formation. The overall technology and circuit design are, in this respect, highly simplified and result in more compact VLSI chips.
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International Journal of Physical, Chemical & Mathematical Sciences, Vol. 2; No. 2: ISSN: 2278-683X (July-Dec. 2013)
The source and drain regions extend down to the buried oxide, yielding reduced junction surface, lower leakage current, and junction capacitance. This offers the opportunity to fabricate CMOS circuits with lower power dissipation in standby and operating modes, improved speed, and wider temperature range. More innovative devices multiple gate MOSFETs, power transistors, sensors, MEMS etc. can be conceived and combined in SOI that intrinsically is a flexible structure, with adjustable thickness for the film and buried oxide. A second class of advantages is related to the superior capability of SOI transistors to face scalability challenges. The key feature is that, unlike the case of bulk Si, the SOI film thickness stands as a tunable parameter for device shrinking: the thinner the film, the lower the drain-tobody field penetration which causes drain-induced barrier lowering (DIBL) effects. Moreover, the limited extension of drain and source regions makes SOI devices less vulnerable to short-channel effects, originated from charge sharing between gate and junctions. SOI devices exhibit superior performance because low leak- age currents and quasi-ideal sub threshold slopes ~60 mV/ decade at room temperature are achievable, hence the threshold voltage can be lowered below 0.3 V.
3. Operating Modes of SOI MOSFETs Depending on the silicon film thickness and the the channel doping concentration, the SOI-MOSFET can be operated in two different regimes: Partially-Depleted (PD) and Fully-Depleted (FD). Fig. 1 (a) and (b) show Partially-Depleted (PD) and Fully-Depleted (FD) structures respectively.
3.1
Partially-Depleted SOI
In Partially Depleted MOSFET, silicon film thickness is greater than the depletion depth. In many ways, the device characteristics of PD-SOI are similar to those of conventional bulk devices. The absence of substrate (body) contacts in PD-SOI results in two parasitic effects, the first one is kink effect or floating body effect, and second one is the presence of parasitic open based NPN bipolar transistor between source and drain. Floating body effect induces a transient effect on circuit delay, making circuit design more complicated. Parasitic bipolar effect results in reduction in breakdown voltage between source and drain, a large off current and a smaller threshold voltage. However, the subthreshold slope and drive current are improved by the presence of the floating-body effect, which improves circuit performance. However, floating-body effects are undesirable and can be controlled by a method such as lifetime adjustment.
Fig. 1 (a) Partially Depleted SOI MOSFET (b) Fully Depleted SOI MOSFET.
3.2
Fully-Depleted SOI
In Fully Depleted SOI, SOI layer is very thin so that the depletion region extends to the bottom SiSiO2 interface and the device channel is fully depleted [6-8]. FD-SOI provides better control of short channel effects and offers a more viable option in terms of scaling potential as compared to PD-SOI. Much lighter doped channel compared to bulk or its PD counterpart, results in less mobility degradation due to impurity scattering or high transverse fields. FD SOI does present some drawbacks such as increased series resistance. This issue however, can be solved by using raised source drain extensions. RF figure of merit of FD SOI such as cut-off frequency, noise and transconductance are much better than bulk MOSFET and PD SOI MOSFET, therefore FD SOI MOSFET are more likely to be used in RF CMOS circuits in the next decade. Despite the attractive features of the FD transistor, it appears that PD SOI MOSFET is the best tradeoff and ready to use SOI MOSFET in comparison with bulk. However, Intel has shown some results
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of a 50nm FD SOI transistor demonstrating the benefit of using FD SOI transistor. At the same time ST Microelectronics and IBM which are working on PD technologies, have shown that FD transistors do not permit the use of multiple threshold voltages. Actually, higher threshold voltages are obtained by increasing the doping level of the channel. Also, PD transistors, unlike FD transistors, allow using the technological solutions already developed for bulk transistors from the same technology node.
4. Advantages of the SOI Technology There are a number of advantages of SOI technology as listed below: (i) Lower parasitic capacitances: In regular SOI structures, the source and drain regions extend to the insulator, and only their lateral sides serve as junctions. The surface of such a junction is much smaller than in bulk silicon. Smaller surface leads to reduction in parasitic capacitances, hence for pre-defined power consumption, much denser and faster circuits can be integrated on SOI wafers. (ii) Short channel effect reduction: The short channel effects are associated to the loss of control of the channel by the gate. For a Fully Depleted SOI MOSFET, the space charge in the thin silicon film is well controlled by the gate. Thus, the short channel effects are reduced in comparison with bulk MOSFET. (iii) Small p-n junction leakage current: The p-n junction leakage current in SOI structure is very small because the effective side wall area of the p-n junction is small due to the small thickness of the top silicon layer. This leads to low standby power requirement. (iv) Low Substrate Noise: With the increased integration of digital and analog circuits on the same die, substrate noise issue is dominant in the bulk process. The digital noise can affect the sensitive analog circuits. In SOI technology, the buried oxide layer acts as a dielectric barrier and helps in reducing the substrate noise. (v) No latch-up effect: Bulk CMOS relies on junction isolation between devices, while SOI uses dielectric isolation to surround the entire device sides and bottom. Latch up in bulk CMOS structures is due to the presence of parasitic components as shown in Fig. 2(a). Fig. 2(b) shows that SOI has no wells into the substrate and therefore has no latch up or leakage paths.
(a)
(b) Fig. 2. Latch up effects in (a) Bulk CMOS (b) SOI CMOS.
(vi) Better Integration density: Since SOI MOSFETs do not have a well or a fourth body terminal as bulk devices do, the isolation for n- and p- MOSFETs is smaller and the layout occupies about 30% less area than that of bulk devices. This is evident from the comparison between the layout of the bulk CMOS inverter and that of an SOI inverter shown in Figs. 3(a) and (b) respectively. It can be seen from Fig. 3(b) that SOI occupies small layout area and hence improves integration density. (vii) High resistivity substrate compatibility: SOI technology offers a natural protection against latch-up, thus it becomes possible to use high resistivity substrates. Such substrates offer new possibilities for wireless technologies. (viii) Better temperature sensitivity: SOI CMOS is much less sensitive to temperature than bulk CMOS. In all SOI processes, the leakage to the substrate is obviously suppressed. (ix) Radiation hardness: An important motivation for developing SOI technologies is due to their excellent tolerance towards transient radiation effects.
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International Journal of Physical, Chemical & Mathematical Sciences, Vol. 2; No. 2: ISSN: 2278-683X (July-Dec. 2013)
(a)
(b) Fig. 3. Layout of (a) Bulk CMOS inverter and (b) SOI CMOS inverter.
Fig. 4. i) single gate; ii) double gate; iii) triple gate iv) quadruple gate (or GAA).
5. Different Gate Configurations for SOI Devices Fig. 4 shows the existing gate configuration for thin-film SOI MOSFETs: i) single gate ii) double gate iii) triple gate iv) quadruple gate (or GAA). It has been proved that the transconductance and drive current of the double-gate, triple-gate and quadruple-gate devices is approximately two, three and four times that of a single-gate device, as could be expected [9]. It is also observed that the conductance and drive current of Pi-gate device are 3.2 times that of the single-gate device [10].
6. Conclusion Advantages of SOI MOSFETS over conventional CMOS were reviewed. Different types of SOI MOSFET are discussed briefly Multiple gate SOI are claimed to be more immune to short channel effects than bulk silicon MOSFETS. This feature would permit a much greater scaling down of these devices than ever imagined in conventional MOSFETS.
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[7] Jiao Z., Salama A.T., A Fully Depleted Delta Channel SOI NMOSFET, Electrochem.Society Proceedings, vol. 2001-3, p. 403-408, 2001. [8] Denton J. P. and Neudeck G. W., “Fully depleted dual-gated thin-film SOI P-MOSFET’s fabricated in SOI islands with an isolated buried polysilicon back gate,” IEEE Electron Device Lett., vol. 17, pp. 509–511, Nov. 1996. [9] Colinge J. P., Gao M.H., Romano A., Maes H., Claeys C., Silicon-on-insulator `gate-all-around' MOS device, Technical Digest of IEDM, p. 595, 1990. [10] J. T. Park, J. P. Colinge, and C. H. Diaz, “Pi-gate SOI MOSFET,” IEEE Electron Device Lett., vol. 22, pp. 405–406, Aug. 2001.
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