THE EVN-MarkIV VLBI DATA PROCESSOR R. T. SCHILIZZI1, W. ALDRICH2 , B. ANDERSON3 , A. BOS4 , R. M. CAMPBELL1 , J. CANARIS5 , R. CAPPALLO2 , J. L. CASSE1∗ , A. CATTANI6 , J. GOODMAN2 , H. J. VAN LANGEVELDE1, A. MACCAFFERRI6 , R. MILLENAAR4, R. G. NOBLE3 , F. OLNON1 , S. M. PARSLEY1 , C. PHILLIPS1, S. V. POGREBENKO1 , D. SMYTHE2 , A. SZOMORU1 , H. VERKOUTER1 and A. R. WHITNEY2 1 Joint Institute for VLBI in Europe, Dwingeloo, The Netherlands 2 MIT Haystack Observatory, Westford, MA, U.S.A. 3 Jodrell Bank Observatory, University of Manchester, U.K. 4 ASTRON, Dwingeloo, The Netherlands 5 Xilinx Corp, Albuquerque, NM, U.S.A. 6 Institute of Radio Astronomy, Bologna, Italy (∗ author for correspondence, e-mail:
[email protected])
(Received 19 September 2001; accepted 13 February 2002)
Abstract. A functional description is given of the new 16-station MarkIV VLBI data processor for the European VLBI Network. The data processor can operate in many configurations including sensitive continuum modes, line modes with unprecedented spectral resolution, and wide field imaging and pulsar gating modes. The EVN-MarkIV processor was developed by an international European/U.S. consortium. Several similar processors are deployed in both Europe and in the U.S. Keywords: data processing, instrumentation, radioastronomy, tape recorder, VLBI correlator
1. Introduction Very Long Baseline Interferometry (VLBI) is an observing technique by which signals from a number of radio telescopes at different locations over the world can be combined to produce, after processing, images of cosmic radio sources with extremely high angular resolution (Kellermann et al., 2001). The radio signals received at each individual telescope are saved onto magnetic tape in one of a number of well-defined formats, for example the Mark IV format (Whitney, 1998), and thereafter decoded and combined (correlated) in a VLBI data processor like the one described in this article. Construction of the EVN MarkIV Data Processor was initiated by the European Consortium for VLBI which manages the European VLBI Network (EVN), a distributed large scale facility comprising most of the radio telescopes in Europe (Schilizzi, 1995). The primary contributors to the design of the processor were the EVN institutes and Haystack Observatory in the U.S.A. The EVN documents can be found on the web at http://www.jive.nl. The MarkIV Memos can
be obtained as a hard copy from
[email protected]. Experimental Astronomy 12: 49–67, 2001. © 2002 Kluwer Academic Publishers. Printed in the Netherlands.
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Figure 1. The Data Processor control room at JIVE showing the row of 16 DPUs in the background. In the middle of the row of DPUs are the oscilloscopes displaying the 16 eye patterns for monitoring the recording and the Data Distributor. The Work Station in the middle foreground is the Correlator Control Computer. The correlator is installed in a separate room and not shown in the picture.
It is operated for the EVN by the Joint Institute for VLBI in Europe (JIVE, Dwingeloo, The Netherlands, see Figure 1), and was officially inaugurated in October 1998. The processor allows the simultaneous correlation of data from up to 16 stations, i.e. 120 cross-correlations and 16 auto-correlations. The Data Playback Units (DPU) can replay data in MkIIIA, VLBA and MkIV formats and they have a maximum data playback rate of 1 Gbit/sec/station with 2 headstacks in MkIV mode. The maximum input data rate to the processor is therefore 16 Gbit/sec. The correlator uses the X-F algorithm (the data is first cross-multiplied (correlated) and then Fourier transformed) for the flexibility it provides in trading lags for baselines. It is based on a new custom VLSI correlator chip developed for this purpose. The architecture is station based, i.e. all station-based parameters are embedded in the data stream. It has a recirculation option for improved spectral-line processing efficiency and a gating option for pulsar observations. The overall block diagram of the EVN MkIV Data Processor at JIVE is shown in Figure 2. The individual blocks are described in later sections of the paper. A companion paper (Whitney et al., 2002) describes the architecture and algorithms for Mk4 VLBI correlators. Each DPU is equipped with 2 headstacks yielding 64 simultaneous tracks. By moving the headstacks across the tape, 6 passes (6 forward and 6 reverse) can be recorded. Each track is able to replay data at a maximum of 16 Mbits/sec/track i.e. 8 MHz per track, yielding a total of 1024 Mbits/sec per
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Figure 2. Simplified block diagram of the EVN MkIV Data Processor.
DPU. The data from the DPU passes to the Station Unit (SU), which reconstructs (i.e. de-multiplexes, de-barrel-rolls, etc.) the data streams as required and passes the reconstructed data streams to the Data Distributor. Data transfer takes place via high frequency link modules (Serial Links). A central clock in the Test Synchronisation Pulsar gating Unit (TSPU) synchronizes the data streams. The correlation process is controlled asynchronously via Ethernet by the Correlator Control Computer (CCC) which sends control messages to the real time processors (HP-RT or PSOS) in the SUs, TSPU, Data Distributor Unit (DDU) and Correlator Unit. The DPUs are controlled from the Station Units via an RS232 line. The diagram shows a ‘Tape Handling System’ which is in fact a vertical storage conveyer system which is used to move the tapes between ground level and the basement where the data processor is located, and at the same time provides storage space for approximately 1800 tapes in their protection boxes. The block diagram includes a number of work stations used to control the entire correlation process.
2. Data Playback Units The DPUs are longitudinal tape recorders which have been designed and built at Penny and Giles Data Systems Ltd (now Metrum Information Storage Ltd, U.K.). The DPU differs from the Honeywell 96/MkIV system (in use all over the world) in that it does not use vacuum to provide the tape tension but spring-loaded tension arms. The guiding scheme is mechanically different, but it is also (this is a requirement) based on tape-edge guiding. The DPUs have all been equipped with two triple cap headstacks (Casse et al., 1998) and can cope with both thick and thin tapes. This latter feature requires, however, a change of the tape tension from
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220 grf (gramforce, thin tape) to 320 grf (thick tape), a process that takes about 10 min in total. The main features of the playback units are summarized below: – – – – –
Replay data with VLBA, MarkIIIA, MarkIV formats. Tape thickness: 13 and 26 microns. Tape width: 1 inch. Tape length: 18 000 foot (thin tape) and 9000 foot (thick tape). Maximum reel diameter: 14 inch. Headstack: max 4, 36 heads/headstack (2 headstacks with 32 heads implemented). – Tape speeds: 80, 160, 320, 330, 135, 270 ips. – Drive acceleration: 40 ips/s. – VLBA control instruction set (Cappallo, 2000). The signals received at the heads are amplified in low noise amplifiers and passed through an equaliser section which can handle the three bandwidths implemented, 2, 4 and 8 MHz. The interface to the station unit is via balanced ECL lines. A head peaking mechanism can be switched on from the CCC. With this feature on, the heads are forced to follow a pre-selected written track. Figure 3 shows a schematic of the tape path superimposed on the photograph of a number of DPUs. The path is mirror imaged when compared with a Honeywell system. The consequence is that the tape edge that needs to be guided is not located on the deck side. This called for a different design of the guiding mechanism. The tape edge guiding mechanism is located as close as possible to the headstacks on the precision plate (Figure 4). As shown in the picture, the tape passes first two adjustable guides which are tilted vertically (one up and one down) in order to make the tape move away from the tape deck by about 40 micrometers. This shift is then removed by pushing back the edge of the tape with the guiding caps. Measurements have shown that a guiding accuracy of a few micrometers can be achieved over the whole length of the tape using this procedure. Except for the tilted posts, all guides are perpendicular to the tape deck. The same applies for the capstan, the reels and the tension arms. The lateral position of the tape is defined by the reaction of the tape edge under the force pushing on it via the guiding cap and the tape tension. Measurements have shown that the pressure applied to the tape edge for a well adjusted tape path is smaller than 1 grf so that no tape edge damage is expected. This was confirmed using a mathematical model for the tape path (Casse, 1999). The adjustment of the tape path is of great importance in order to prevent tape damage in particular when running thin tape at maximum velocity (8 m/s). The procedure for the adjustment is complex and time consuming (Buiter, 1999). In order to be able to read multiple passes, the two headstacks can be moved with micrometre accuracy across the tape by a DC motor controlled by a longitudinal positioner (LVDT). The tracks written are 38 micrometers wide. The
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Figure 3. Photograph of a number of DPUs complete with their Station Units underneath. Superimposed is a schematic showing the main elements of the tape path including 4 headstacks. The two bottom headstack positions have, however, not been implemented.
distance between track centres is variable. The most common transverse format uses 14 × 32 = 448 tracks.
3. Station Units A Station Unit (SU) collects the data from the DPU, decodes them and sends them in the correct format to the correlator. It consists of a 19 inch crate as shown in Figure 5. The SUs belong logically to the DPUs: each SU is installed in the bottom section of its DPU. The SUs were designed by Penny and Giles Data Systems Ltd and replicated by Allied Signal Inc. The SUs are responsible for reconstructing the raw data from the DPUs (up to 64 tracks delivering data at a maximum rate of 16 Mbps). The SU must finally
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Figure 4. Photograph of the precision plate. From left to right, the picture shows the tape running past the tilted post, the guiding post with the guiding cap, the tape edge adjusting jig, headstack number 1 and on the right hand side, the capstan.
Figure 5. Front view of a Station Unit showing the various modules described below.
Figure 6. Simplified schematic of a Station Unit (in the dashed line box) which shows the organisation of the unit. As can be seen in the figure, control of the DPU is one of the tasks of the SU Control Computer (SUCC).
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produce channelised data compatible with the format of the correlator. Each SU fits in one crate that houses 17 boards (see Figure 5). This compact arrangement has been made possible through the extensive use of Field Programmable Gate Arrays (FPGA) and local intelligence on most of the boards. Figure 6 shows a simplified schematic of a Station Unit and its 17 boards: 2 data input modules, 8 track recovery modules, 1 channel recovery module, one phase cal module, two delay modules controlled by one delay control module, a Station Unit Interface Module (SUIM) and the SU Control Computer (SUCC) programmed in PSOS+. The 64 output signals from the DPU can be flexibly routed (in the Data Input Modules) to the Track Recovery Modules where the clock is first recovered from each of the received 64 tracks of data. The clock-recovered data is then decoded for each track by an FPGA which detects embedded synchronisation words, validates CRC, and counts parity errors. The header data is analyzed by an embedded microprocessor, and the data itself is placed in a large RAM area (512*9 kbit RAM per track). The track data can then be loaded synchronously into the Channel Recovery Module where it is converted from track data into channel data and the applied modulation removed. This process undoes multiplexing or barrel-rolling if applied during data acquisition. The outputs of the de-formatter module are then replicas of the sample streams from each recorded video-channel, and are at rates up to 32 Msamples/sec each. For 2-bit sampled data, the sign and magnitude data streams are treated independently. Phase calibration data will be extracted in the Phase Calibration Module and read by the CCC. Each data-stream is then delayed relative to the time written on the tape in the Delay Memory Module according to a polynomial model (Anderson, 1994) derived from a geometrical model on the CCC. The Delay Memory Modules are controlled by a Delay Control Module. The last board in the SU is the Station Unit Interface Module. This module receives the system synchronisation signals, test frames and pulsar gate waveforms from the Test Synchronisation Pulsar Unit (TSPU). It is able to inject test data into the input of the SU, perform pulsar gating of the channel data, and calculate the count statistics for all channel streams. This feature is currently not yet software implemented.
4. Test Synchronisation Pulsar Gating Unit (TSPU) The TSPU (Anderson et al., 1993; Bos, 1993) consists of an independent crate with its own HPRT system linked to the Correlator Control Computer. The crate houses a number of boards: the Clock Module (CLKM), the Test Synchronisation Pulsar Gating Module (TSPM) and splitter modules to feed the various units (Data Distributor, Correlator and SU’s) of the processor. Its tasks are to:
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Figure 7. Simplified schematic of the TSPU.
(a) Reproduce testpatterns in the form of the MkIV formatted tracks; 8 independently defined tracks may be reproduced simultaneously; (b) Produce the system synchronization signals: 10 and 32 MHz system clocks, 1 pps SYSTICK for the SUs, DDU and the correlator, and period programmable BOCF. (c) Generate 16 independently programmed Pulsar Gate waveforms. (d) Deliver the Test Frames, Pulsar Gates and Synchronisation signals to the SUs via serial links. The TSPU (Figure 7) communicates with the crate control computer via the VME bus.
5. Data Transmission and Synchronisation The transfer of data between the Station Units and the Data Distributor and also between the Data Distributor and the Correlator takes place via Serial Links (Smythe et al., 1993). Each link has 4 lines that transmit the sign, magnitude and validity of the data as well as the BOCF (Beginning Of Correlator Frame) which provides timing for the correlation process. The format of the data leaving the SUs (correlator frame) consists of a header which contain delay and phase control parameters for the next data frame and data (sign, magnitude and validity). The output from each serial link module consists of eight 1 or 2-bit data channels at rates up to 32 Msamples/sec each. The data is synchronously recovered by the ‘receive chip’. The synchronisation between the various parts of the hardware and the real time software is coordinated by a clock signal supplied by the central reference clock in the TSPU.
Figure 8. Schematic showing the scheme used for transporting data between the various units of the data processor. The transmitters and receivers are equipped with the HP Gigabit rate chip set HDMP-1000.
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Figure 9. Schematic showing the internal configuration of a correlator chip. The chip consists of 8 complex correlator modules (B0 to B3 and A0 to A3) with 32 lags each, connected to the X and Y signals to be correlated. The correlator modules can be flexibly connected to suit the needs of the observing program.
6. Correlator system A special purpose correlator chip forms the heart of the correlator system (Bos, 1993). A full-custom 200 pin VLSI CMOS chip (Canaris et al., 1993; Bos et al., 1996) was designed as at the time of the start of the project FPGAs were not yet in state to meet the specification which called for about 1 000 000 gates at a speed of 64 MHz. The correlator chip features 512 lags, which can be rearranged internally into 16 real or 8 complex independent correlator cells with 32 or 16 lags, respectively. It operates at a 32 MHz clock rate. It supports correlation with 2-bits/sample (4-level) with an option for a validity bit for each sample (local validity) or for each correlator cell (global validity). Figure 9 sketches the hardware configuration inside such a correlator chip. The Correlator consists of 4 crates (correlator units) each populated with 8 correlator boards and a Real Time Processor in the front and 2 input boards and a control board in the back of the correlator rack (see Figure 10). The input boards are populated with 8 multiplexed serial links of the receiver type. The control of the correlation process takes place via the on-board processor which communicates via the Ethernet with the control computer. Each of the 8 complex correlator sections includes a header capture circuit block that allows capture of station-based delay and phase tracking parameters embedded in the serial data streams from the Station Units. These parameters are used to
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Figure 10. Simplified diagram showing the hardware configuration of the correlator section. The 4 correlator units can be seen in the background in Figure 11.
control the phase rotator and vernier delay in each correlator module. The 8 internal complex – correlator cells each include a full 3-level 32 – quadrature phase digitalfrequency synthesizer used to compensate for differential fringe rate. Each correlator board (Goodman, 1993) contains 32 of the VLSI correlator chips designed at the Haystack Observatory and implemented at the University of New Mexico. Each board has access to sixty four 2-bit data streams at a rate of 32 Msamples per second. With the correlator chips connected in series, each board yields 16384 complex lags. It supports up to 120 channel baselines, processing at 32 Msamples/sec/baseline. The flexibility offered by the hardware of the correlator can be characterized by five parameters: the number of basebands B, the number of polarisations P, the recirculation factor R (1 to 8), the number of stations S, and the number of spectral frequency points F.
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Figure 11. Front view of one of the four correlator units each of which holds 8 correlator boards. One of the four correlator boards installed has been pulled out and shows the 32 correlator chips. The 4 correlator units can be seen in the background.
The configuration of the correlator in local validity is defined by: B.P.F.S2 = 131072.R Table I shows a number of possible configurations allowed by the system (for 16 MHz basebands, local validity, and no recirculation).
7. Data Distributor The Data Distributor (Millenaar, 1997) is responsible for distributing the signals from the Station Units to the Correlator Modules in a flexible manner to allow the correlator to operate at high efficiency under all conditions including the case when the observed bandwidth and hence the data rate is small. It also provides the ‘recirculation’ mode (not yet operational) with a factor of up to 8 to support spectral line processing with higher resolution by using redundant processing capacity for signal bandwidths smaller than 16 MHz, polarisation processing and multiple field of view processing. This allows, for example, a maximum of 8192 channels per baseband for one polarisation and one baseband for a 16-station observation. The usable capacity of the correlator is currently limited by the output rate, which is determined by the integration time. The current lower limit of 1 second will
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TABLE I A number of possible configurations allowed by the system Number of stations S
Number of polarization subbands P
Number of frequency subbands B
Number of frequency points F
8 8 8 8 16 16 16 16
1 4 2 4 1 4 2 4
8 8 1 1 8 8 1 1
256 64 1024 512 64 16 256 128
be reduced to a fraction of a second by the introduction of the Post Correlation Integrator, now in development at JIVE. The Data Distributor (DD, Figure 12) consists of one crate controlled by an HPRT board. The signals from the SU enter the DD via the pre-selector board which houses switching networks and the recirculation memory. The pre-selector board is followed by the post-selector board which consists of a complex crossbar switching system. Both types of boards are populated with multiplexed (transmitter or receiver) serial links for the transmission of data.
8. Control of the Correlation Process The control of the correlation is handled by the Correlator Control Computer (CCC). The function of the Processor Control Software (Noble, 1994) is to provide the processor with the necessary instructions in order to perform the correlation of a number of tapes using data provided by the telescopes, data related to the observation and data related to the telescope hardware (from the data base). A layer of software in the unit controllers interfaces the Processor Control Software to the hardware (the station units, correlators (including the data distributor), TSPU, Tape Handling System, etc.). Above this layer are a number of other layers that handle individual tapes, individual telescopes, and finally the overall control of the job. Knitting all the tasks together, is the process Model and Messaging System. One particularly important message is the Correlation Job Descriptor (CJD). This contains the information needed to process an experiment, and is built up from
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Figure 12. Schematic of the Data Distributor. The recirculation memory allows storage of ‘new’ data in a memory (for example A or B) while the ‘old’ data is repeatedly processed. The crossbar switch module provides the flexibility for connecting the channels to the correlator.
the observing schedule in VEX (VLBI EXchange) format augmented by station logs and other information. The CJD is passed to all of the software layers involved in processing an experiment, each one adding or extracting the information it needs. Beyond the running of individual jobs, there is the overall control of the Correlator, database handling and other sections of the Control Software. Figure 13 illustrates the numerous tasks which have to be performed by the Correlator Control Computer. The purpose of the CCC is to control the actions of the Correlator and to act as the interface to the Operators. The software has been written in C++ and uses Object Oriented Methodology. A number of documents describing the system are listed in the References. A Unix work station has been adopted for the CCC in order to provide flexibility and to support the Graphical User Interface (GUI). Because Unix does not provide any real-time capability, all time-critical operations are carried out by the realtime processors in the Station Units, Data Distributor and Correlator. The system is designed to run more than one job at a time to make maximum use of the Correlator’s hardware resources. The control of the correlating process is achieved by downloading a set of commands, marked for execution at particular times, to the real-time processors before the processing job starts. Once a job is running, CCC’s involvement is then largely restricted to handling status messages and some data (phase calibration and sampler statistics). Post-correlation software is required for the distribution and archiving of the correlator output as well as the tools for data inspection (Van Langevelde, 1996).
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Figure 13. The interactions that take place between observers, observing stations and the Data Processor for the correlation of an experiment.
These have been developed on the aips++ platform. A conversion tool converts the raw correlator data, together with auxiliary data, directly into aips++ (and from there to classic AIPS). This software must also take care of the quality control and distribution of the correlated data. This software runs on a separate platform called the Evaluation and Export Engine (see Figure 2).
9. Conclusions The official inauguration of the EVN Data Processor at JIVE took place on 23 October 1998. It took more than six months before standard data correlation began using the simplest modes of operation, and 15 months before the first scientific paper based on data correlated at JIVE was published (Van Langevelde et al., 2001).
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More complex modes have been introduced since, and continue to be introduced as resources allow. Looking back on the project as a whole, one can say that the international collaboration and the distributed development involved went remarkably smoothly considering the complexity of the project. Crucial elements in this success were the definition of detailed interface specifications at the start of the project, the organization of regular design review meetings throughout the project, and good communication at other times. The 7 years taken to complete the project (1993– 1999) is typical for state-of-the-art processors for radio interferometry data. An important factor in allowing new modes to be implemented in a relatively seamless way has been the use of Object Oriented Methodology in the software driving the high level operation of the data processor. A number of problems took time to solve including the guiding of the tape through the Data Playback Units (DPU) to the required accuracy, and elimination of cross-talk in the Station Units (SU) generated by the close physical proximity of many complex VLSI chips. The problems with the DPUs and SUs were exacerbated by the fact that the company involved changed hands twice during the course of the project. The key element of the correlator itself, the correlator chip, required only one iteration in the manufacturing cycle after the prototype had been tested. The mode of operation using a tape speed of 320 ips has not yet been implemented since the sensitivity of the magnetic heads at that speed turned out, unexpectedly, to be marginal. Future generations of VLBI systems and data processors are likely to abandon tape technology in favour of PC hard disks for storage and transport, and, on the longer term, real-time optical fibre connections from the telescopes to the data processor.
Acknowledgements The design and prototyping of the hardware and the software for the EVN MkIV Data Processor has been an international endeavour which took place under the auspices of the International Advanced Correlator Consortium (IACC). Within the IACC, the design tasks were equally divided between the European and US groups participating in the Consortium, the Joint Institute for VLBI in Europe (JIVE), the Stichting Astronomisch Onderzoek in Nederland (ASTRON) and the NASA Goddard Space Flight Center representing itself, the Haystack Observatory, the Smithsonian Center for Astrophysics and the University of New Mexico. Copies of the data processor described in this paper, with variations, have been made for Haystack Observatory, USNO and MPIfR (Max-Planck-Institut für Radioastronomie). The design of the Station Unit, the responsibility of JIVE, was contracted to Penny & Giles Data Systems (P&G, now Metrum Information Storage Ltd) in the U.K. The replication was done by Allied Signal Inc. in the U.S.A. The Correlator
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hardware was primarily a task for the Haystack Observatory with a contribution from ASTRON. The custom-made correlator chip was designed at Haystack Observatory, laid out by the NASA Space Engineering Center (SERC) for VLSI System Design at the University of New Mexico and fabricated by Hewlett Packard Company. The Station Unit Interface Module (SUIM) which links the Station Units to the correlator and the central clock system and also provides test and pulsar gating waveforms (TSPU) was the responsibility of JIVE in Dwingeloo with much of the work for the design and replication carried out by the Institute of Radio Astronomy (IRA) at Bologna. The Data Distributor which links the Station Units to the Correlator module was the responsibility of ASTRON while the DPUs were purchased from P&G. Development of the high level control software was carried out by the Jodrell Bank Observatory in the U.K. Many people participated in the design, construction and testing of the Data Processor. The team developing the software in Jodrell Bank included Peter Shepherd, Paul Maguire and Silvia de Beer. The software for the Station Unit was designed by Phil Hazell. At the MIT Haystack Observatory, Ken Wilson and Peter Bolis helped with the design, replication and testing of numerous modules. Jan Buiter succeeded in optimizing the tape paths of all 16 DPUs. The installation and the testing of the hardware in the control room in Dwingeloo was undertaken by Jan Buiter, Sjouke Zwier and Martin Leeuwinga. Bauke Kramer, Hans Tenkink, Ron Heald and Henk Klijn Hesselink were involved in software development at JIVE. Klaas Stuurwold assisted with the installation and upgrades of the work stations in the network. Special thanks go to Hans Hinteregger and Alan Rogers at the Haystack Observatory for their advice in solving DPU problems and George Peck at the VLBA for helping JIVE with the recording of numerous test tapes. Funding for the design and the construction of the EVN Data Processor at JIVE came from grants from The Netherlands Ministry of Education, Culture and Science, the Institut National des Sciences de l’Univers (INSU/CNRS) in France, and the Wallenberg Foundation in Sweden. Funding for the design efforts at the Haystack Observatory came from NASA, US Naval Observatory, the Smithsonian Institution and the Bundesamt für Kartographie und Geodäsie (Wetzell, Germany). References Anderson, B.: 1994, EVN doc #29, Model calculations for the EVN processor delay model. Anderson, B. and Pogrebenko, S. V. P.: 1993, EVN doc #9, Test/Synchronization, Pulsar Gate Subsystem. Bos, A.: 1993, EVN doc #24, System synchronization in the EVNFRA correlator. Bos, A., Aldrich, W. H. and Whitney, A. R.: 1996, EVN doc #207, The Haystack correlator. Buiter, J.: 1999, EVN doc#106, Tape path and tape guidance adjustment and calibration procedure. Canaris, J. and Aldrich, W. H.: 1993, MkIV memo #225, CMOS Correlator. Cappallo, R.: 2000, VLBA Acq. Memo #238, Recorder controller commands. Casse, J. L., Hinteregger, H. F., Peck, G. and Rayhrer, B.: 1998, MarkIV Memo #144.2, Stepped and triple-cap headstack specification for VLBI Tape recorders.
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Casse, J. L.: 1999, EVN doc #103, Modelling of the tape path of the play back units of the EVNMarkIV Data Processor. Goodman, J.: 1993, MkIV Memo #191, Correlator board hardware specification. Kellermann, K. I. and Moran, J. M.: 2001, Annual Review Astronomy & Astrophysics 2001, pp. 457– 509. Millenaar, R. P.: 1997, EVN doc #60, The EVNFRA Data Distributor unit: Functional description. Noble, R.: 1994, EVN doc #11, Software analysis. Noble, R.: 1994, EVN doc #32, Software analysis: Introduction. Schilizzi, R. T.: 1995, URSI Radio Science Bulletin # 274, Current developments in VLBI astronomy on the ground and in space, pp. 14–28. Smythe, D. and Bos, A.: 1993, EVN doc #15, System data interface specification. Van Langevelde, H. J.: 1996, EVN doc #68, JIVE/EVN correlator output: Format and tools. Van Langevelde, H. J., Pihlström, Y. M., Conway, J. E., Jaffe, W. and Schilizzi, R. T.: 2000, A&A (Letters) 354, L45–48. Whitney, A. R.: 1998, MarkIV Memo #230.2, MarkIIIIA, IV/VLBA formats, recording modes and compatibility. Whitney, A. R., Cappallo, R., Aldrich, W., Anderson, B., Casse, J. L., Goodman, J., Parsley, S., Pogrebenko, S., Schilizzi, R. and Smythe, D.: 2002, in preparation.
