Microelectronic Engineering 88 (2011) 877–881
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Ultradense silicon nanowire arrays produced via top-down planar technology M. Ferri a, F. Suriano a, A. Roncaglia a, S. Solmi a, G.F. Cerofolini b,⇑, E. Romano b, D. Narducci b a b
IMM-CNR, Via Gobetti 101, 40100 Bologna, Italy CNISM and Department of Materials Science, University of Milano – Bicocca, Via Cozzi 53, 20125 Milano, Italy
a r t i c l e
i n f o
Article history: Received 13 August 2010 Accepted 19 November 2010 Available online 13 December 2010
a b s t r a c t A process is developed for the fabrication of vertically arranged poly-silicon nanowires via a rigorously top-down batch process. The technique allows the production of wire arrays with larger linear density (projected on the surface) than those achievable with any of the other proposed top-down processes. Ó 2010 Elsevier B.V. All rights reserved.
Keywords: Silicon nanowires Top-down processing Electrical characteristics
1. Introduction Semiconductor nanowires (NWs) have attracted a large interest in the past years [1–4] for their potential applications in electronics [5], optoelectronics [5], and medicine [6–8]. Silicon NWs, in particular, have been the focus of an increasing interest [9,10] because of their integrability in silicon-device processing. Far from being complete, the list of potential applications includes biochips [11], new-generation electronics [12,13], conductive wires defining the crossbars for molecular electronics [14,15], demultiplexing elements for sublithographic crossbars [16–18], and active elements of Seebeck generators [19,20]. Some of the above applications require single crystalline silicon; for others (those exploiting the majority carriers) poly-crystalline silicon is sufficient (as happens for conductive wires for hybrid inorganic–organic crossbars [14–16]) or even better (as in the case of almost degenerate nanowires as Seebeck generators [19,20]). In this work, the attention will be concentrated on poly-crystalline silicon (poly-Si), of which we exploit its ability to give conformal coverages even in very restricted geometries when deposited from silane monomers at low pressure. Of course, NWs may be prepared using lithographic methods: conventional photolithography (henceforth ‘lithography’ without attributes) combined with controlled overetching allows their cheap production, but the maximum linear density is limited to 105 cm1 by the achievable pitch P of about 100 nm; advanced (electron beam, deep ultraviolet, or extreme ultraviolet) lithography allows the density limit to be extended by a factor of 5–10, but at a huge production cost (due to investments for deep or ex⇑ Corresponding author. E-mail address:
[email protected] (G.F. Cerofolini). 0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.11.034
treme ultraviolet lithography, or to low throughput for electronbeam lithography). If the intended application of poly-Si NWs is consistent with their arrangement in regular arrays, the simple geometry allows them to be prepared via much cheaper non-lithographic techniques (NLTs). These NLTs are generally based on the transformation of a thickness into a width. This operation is convenient when (i) the thickness is controllable on a length scale much smaller than the lithographically producible length scale W, and (ii) the process keeps the width w close to the thickness t of the film. Situation (i) is characteristic of many films, whose thickness is controllable on the nanometre length scale whereas the lithographic definition is on the length scale of 102 nm. Since now on we shall limit to situations satisfying both (i) and (ii), for which non-lithographic features are sublithographic features: w’tW
NLT :t ! w; where the sizes of sublithographic features are denoted with lowercase letters, whereas those of lithographically defined features are denoted with the same capital letters. We shall conform to this convention even in the following. Among the NLTs we mention the superlattice nanowire pattern transfer (SNAP) technique that may be used for the preparation of masks for a subsequent nanoimprint lithography (NIL), and the multi-sidewall patterning technology (MSPT) that instead requires a preliminary pattern defined lithographically. Nanoimprint lithography is a technique for the one-to-one transfer of a pattern from a contact mask to a substrate without using optical projection [21,22]. This technique is emerging as a
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potential successor of advanced lithography because of its simplicity, low cost, high throughput, and high resolution [23]. The reduced complexity of NIL apparati is paid in terms of the difficulty of preparing hard masks with adequate quality. If NIL is addressed to define NWs (rather than to impart a specific shape to the imprinted pattern), the mask can conveniently be produced via SNAP technique. The SNAP is an NLT for the preparation of NIL masks for nanowires [24]. For instance, a contact mask with pitch p of 16 nm was prepared growing a superlattice on a single crystalline substrate by molecular beam epitaxy, cutting the sample perpendicularly to the surface, polishing the newly exposed surface, and etching selectively the different strata of the superlattice [25]. The MSPT, instead, is essentially based on the repetition (in additive or multiplicative fashion) of the sidewall patterning technique (SPT), an age-old technology originally developed for the dielectric insulation of source-and-drain metal electrodes from the gate of field-effect transistors [26–33]. Wire arrays with pitch p on the length scale of 20 nm seem at the reach of this technology: nanowires with width of 7 nm [27] and arrays with p ¼ 35 nm have indeed been reported [28,29]. If p is the pitch of the NW array (as results from SNAP-NIL or MSPT), the linear density d is given by d ¼ p1 . Higher densities are producible, for assigned pitch, only arranging the NWs not only horizontally but also vertically. As far as the NW arrays resulting from SNAP-NIL and MSPT lie in a plane, these techniques succeed in the production of higher densities only arranging the NW arrays in more layers. The production of N layers requires however the repetition of N unit operations and, consequently, the multiplication of production cost by the same factor (and likely implies a loss of yield). In this work, we shall demonstrate that a vertical organization of the NW arrays is possible via a non-conventional use of otherwise fully conventional planar technology. The demonstration will be carried out preparing three-dimensional arrangements of polySi nanowires, where the NWs are disposed with vertical separation on the 30-nm length scale and horizontal separation on the deep sub-micrometre length scale.
Fig. 1. Cross-sections (left) and plan views (right) of the structures resulting in the preparation of the vertical wire arrays.
2. Vertical organization of the nanowire array The basic idea consists in the exploitation, by controlled etching and filling, of the recessed regions resulting from conventional IC processing [34]. 2.1. Sketch of the idea The process starts with the formation of a multilayered stack of insulators A and B over a suitable insulating substrate C as sketched in the following:
zffl}|ffl{ zffl}|ffl{ zffl}|ffl{ Ck AjBj 1 AjBj 2 AjBj N ; |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
(a) sequential deposition of N SiO2 —Si3 N4 bilayers, (b) definition thereon of a deep trench, (c) formation of N recessed regions per trench side by partial selective etching of the SiO2 layers, (d) conformal deposition of a poly-Si film sufficiently thick to fill completely the recessed regions, and (e) partial selective etching of the poly-Si film for the duration required to etch silicon from the horizontal regions. 2.2. Proof of the idea
ð1Þ
t N ¼NðtA þt B Þ
where tA and t B are the thicknesses of films A and B, while t N is the thickness of the stack: t N ¼ Nðt A þ t B Þ. The materials are characterized by the existence of a selective etch for A with respect to B; C may coincide with A or B. To be concrete we shall think of A as SiO2 , of B as Si3 N4 , and of C as a thick SiO2 layer. The thicknesses of A and B are not critical; however for reasons of concreteness we shall fix them to t A ¼ 30 nm and tB ¼ 20 nm, respectively. The number N of bilayers forming the film is such to allow the formation by directional etching (e.g., via reactive ion etching, RIE) of a deep trench with depth tN . The overall process, sketched in Fig. 1(a)–(e), involves the following steps:
The process was practically implemented starting from n-type silicon (1 0 0) wafers with resistivity of 0:2—1 X cm and initiated with the growth via wet oxidation at 1000 °C of an SiO2 layer with thickness of 120 nm. After that an Si3 N4 film with thickness of 50 nm was grown by low-pressure chemical vapour deposition (LPCVD) at 780 °C in SiH2 Cl2 and NH3 atmosphere and partially oxidized at 1100 °C in wet atmosphere in order to create a thin SiO2 layer. The reiteration of this procedure produced a stack of alternating Si3 N4 and SiO2 layers. This stack was patterned using conventional photolithography and a reactive ion etching RIE. A diluted water solution of HF ðHF : H2 O ¼ 1 : 20 vol:=vol:Þ was used for the selective etching of SiO2 and the duration of the etch
M. Ferri et al. / Microelectronic Engineering 88 (2011) 877–881
was tuned to form recessed regions in the sides of the trench of controlled length. A conformal LPCVD of poly-Si via pyrolytic decomposition of SiH4 was then used to fill the recessed regions and was completed with the formation on the outer surfaces of a 20-nm thick film. Since the resistance of undoped poly-Si NWs is unmeasurably high, the poly-Si was doped to prepare highly conductive nanowires. The doping involved a phosphorus predeposition from POCl3 source at 920 °C followed by an annealing in an inert ðN2 Þ atmosphere at 1100 °C. A subsequent oxidation in dry O2 atmosphere for a time sufficient to oxidize completely the outer surfaces produced thus the complete dielectric insulation of each nanowire from the others. The NWs were then contacted first etching the SiO2 with a diluted aqueous solution of HF and then depositing a conventional Al:Si(1%) film in a sputtering system so designed as to permit a reliable step coverage even on nearly vertical walls. At last, the film was etched with a mask permitting (i) the access to the parallel of 1, 2 or 4 lines (each containing 8 NWs, 4 per side), (ii) the determination of the resistance for different wire lengths, and (iii) two- and four-probe resistance measurements. The mask is shown in Fig. 2. The structures at several levels of process were characterized using a field emission scanning electron microscopy (SEM) whereas the contacted NWs were characterized electrically. Images of the structures with N ¼ 4 resulting after steps (b) and (c) are shown in Fig. 3, together with the separated poly-Si NWs resulting after the partial oxidation of the poly-Si deposited in step (d). SEM inspection of the recessed regions resulting after step (c) showed defect-free recessed regions on a length scale of 5 lm (Fig. 4, side views), whereas Fig. 5 shows that overetching the hosting structure released wires which do not show any loss of continuity over distances of the order of 20 lm. Clearly enough, SEM inspection is insufficient to guarantee the electrical continuity on a macroscopic length scale (say a few centimetres) for which an electrical characterization is required. Determining the electrical characteristics of the NWs was found easier than expected. Fig. 6 shows the current–voltage I—V characteristic of the parallel of 16 NWs running in two adjacent lithographic lines measured between the central contacts. The graph confirms that the wires have indeed a resistive behaviour. Fig. 7 shows that the resistance of the parallel of n NWs increases in proportion to their length L (in the interval 1–4 mm) and decreases with n1 .
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Fig. 3. Comparison of the cross-sections, as result from SEM inspection, of the structures produced after step (b), top, step (c), middle, and after the partial silicon oxidation between steps (d) and (e), bottom.
Fig. 4. SEM side views at different magnifications of the recessed regions resulting after step (c).
Fig. 2. Plan view of the mask defining the resistors (left) and cross-section of one line side, with highlighting of one nanowire (right).
Taken together, these data can be interpreted in terms of electrical continuity of the NWs, with no failure in a sample of 52 NWs each of length 4 mm. Two-point measurements on NWs in lines with length up to 10 cm confirmed the continuity of the NWs even on this length scale.
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Fig. 5. SEM images at different magnifications of the nanowire after detachment from the hosting structure. Fig. 8. SEM image of the cross-section of the recessed regions formed at the side of a sublithographically defined seed.
At last we note that although the process was developed in an academic facility with 2-lm lithography, it can be scaled down, as shown in Fig. 8, without any appreciable degradation to a line width of approximately 0.2 lm using SPT for its definition. The reproducibility of the process was verified in three consecutive successful runs. In one of them we also checked that the process continue to work even when the SiO2 and Si3 N4 thickness and the depth of the recessed regions undergo minor (say ±30%) variations. 3. Limits Fig. 6. Current–voltage I—V characteristic of the parallel of 16 NWs running in two adjacent lithographic lines measured between the central contacts.
If the etch produced truly vertical sidewalls, the linear density of nanowire would be limited by the trench depth alone. However, the RIE results in trenches with finite aspect ratio, that limits the producible NW density. To calculate the maximum achievable projected linear density, we consider the loss of verticality due to the incomplete anisotropy of the RIE. To simplify the discussion, we assume that the RIE produces planar sidewalls so that the actual shape can be represented with the rectilinear one shown in Fig. 9. Denoting with bN the lateral loss of geometry due to partial etching anisotropy, the (lithographically defined) pitch PN is given by
PN ¼ W þ 2bN þ s;
Fig. 7. Dependence of the resistance (two-point measurements) on NW length for the parallel of 8, 16 and 32 nanowires (1, 2 and 4 lines).
The comparison of two-point and four-point measurements gave substantially equivalent results, with the four-point measurements regularly smaller than two-point measurement by less than 0.2%. This small difference is accounted for in terms of contact resistance. Taking into account the NW cross-section ð75 31 nm2 , see Fig. 2), the NW resistivity is around 2 103 X cm. This value, compared with the resistivity of single crystalline silicon doped in the same condition, 5 104 X cm, is surprisingly low, especially if one considers the scattering effects of the confining walls and crystal distribution (bamboo-like or pearl-necklace-like?) along the nanowires.
Fig. 9. Geometrical parameters defining the trench.
ð2Þ
M. Ferri et al. / Microelectronic Engineering 88 (2011) 877–881
where s is the separation between the opposite sides at the base of the trench. Inserting Eq. (2) into d ¼ 2N=P N , remembering the symbols in (1), and denoting wit R is the aspect ratio of the trench ðR ¼ t N =bN Þ, one gets
d¼
1 R ; 1 þ N =N t A þ tB
ð3Þ
where
ðW þ sÞR : N ¼ A 2 t þ tB
ð4Þ
Eq. (3) is especially interesting because shows that in the limit of large N ðN N Þ the density becomes totally independent of lithography and is controlled by the aspect ratio R and sublithographic pitch ðt A þ t B Þ only:
R N N ) d ’ A : t þ tB
ð5Þ
The vertical arrangement allows thus a magnification by a factor of R of the maximum density, ðt A þ t B Þ1 , achievable for a planar arrangement of closely packed nanowires. In our experiments we obtained R ¼ 17 (see the top of Fig. 3); for this value Eq. (5) predicts a maximum linear density, of 3:4 106 cm1 , larger by a factor of 6 than the most dense structure hitherto presented [25]. Even larger values are expectedly achievable in industrial facilities. Of course, this value is achieved for N=N 1. To manage relatively thin multilayers N must be larger, but not too larger, than N (say N ¼ 2N ) and N must be minimized. To minimize N , both s and W should take their least allowed values smin and W min , so that Eq. (4) gives
Nmin ¼
ðW min þ smin ÞR : 2 tA þ tB
ð6Þ
In particular, s is limited from the below by a separation allowing all wires to be contacted by the crossing wire; conceptually it can be reduced to 0, smin ¼ 0. W min is instead limited by the stability of the structure in the various process steps. In our experiments (however limited by our lithography to a minimum feature size of 1.5 lm and to 2 and 4 layers) we did not observe any change in the upper structure with W and N. Anyway, W cannot be smaller than 2dk þ t B , where dk is the extension of the nanowire cross-section along the surface and the thickness t B , supposedly sufficient to guarantee the dielectric insulation between the same array, is expectedly able to guarantee the dielectric insulation between adjacent nanowires on the same plane at the top of the trench. Assuming W min ¼ 2dk þ tB , Eq. (6) becomes
Nmin ¼
B
A
4. Conclusions In this work, we have demonstrated that vertically arranged nanowire arrays can be fabricated with linear density in excess to 106 cm1 in a rigorous top-down approach and employing conventional IC processes, although in a non-conventional fashion. The demonstration of the feasibility of the process, carried out in an academic facility, was limited to the vertical arrangement of 4 NWs per sidewall; the achievement of the theoretical maximum density requires a production plant endowed with cluster machine or pulsed reactor for the deposition of a sufficiently thick multilayered stack. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
[14] [15] [16] [17] [18]
[19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29]
2dk þ t R : 2 tA þ tB
ð7Þ B
N min
For dk ¼ t ¼ 30 nm;t ¼ 20 nm and R ¼ 20, then ¼ 16: a process carried out on a multilayer with N ¼ 32 (thus employing a 1.6 lm-thick film) would result in a linear density of 3:2 106 cm1 . The use of rectangularly shaped nanowire (with dk t A ) would imply a larger value of N (and thus thicker stacks) but would not impact on the limit density (5) achievable in the limit for N N .
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[32] [33] [34]
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