Very High Data Rate Test Platform for Contactless Smartcard Systems

June 13, 2017 | Autor: Harald Enzinger | Categoria: Wireless Power Transmission, NFC ( Near Field Communication ), RFID and Sensor Networks
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Very High Data Rate Test Platform for Contactless Smartcard Systems

Harald Enzinger

A thesis submitted in partial fulfillment of the requirements for the degree of

Diplom Ingenieur (FH)

Department of Electronic Engineering

University of Applied Sciences Kapfenberg

August 2009

c 2009 Harald Enzinger

All rights reserved.

Abstract This work deals with the development of a new standard for enhanced transmission rates for contactless smartcard systems according to ISO 14443. The aim is to achieve data rates that are significantly above today’s maximum of 848 kbit/s. Contactless smartcards are a form of chipcards that can be accessed over a radio frequency field. The communication is based on inductive coupling and uses a carrier frequency of 13.56 MHz. For the downlink (card to reader) the concept of load modulation is used. Because of the close relation to RFID the first chapter of this work contains an overview on RFID systems. The state of the art of contactless smartcards is presented and an introduction on Very High Data Rates is given. In the second chapter the physical, mathematical, and technical fundamentals of inductively coupled transmission systems are described. This is followed by the presentation of a Matlab based system model in the third chapter. The system modeling contains a description of the channels for up- and downlink by transfer functions and an evaluation of the dependencies on the operation point. The impact of load modulation on the amplitude and phase of the carrier is calculated. The conception of the Very High Data Rate Test Platform is presented in the fourth chapter. It is a hardware setup that allows the generation of various modulation schemes and can be used to validate transmit- and receive concepts. The analog and digital developments for the Test Platform are described in the fifth and sixed chapter. The seventh chapter contains results of measurements that were carried out to validate the functionality of the Test Platform and to characterize the transmissions of up- and downlink. In the final chapter a recapitulation of the achieved results is presented and the next steps in the development process are outlined.

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Kurzfassung Diese Arbeit befasst sich mit der Entwicklung eines neuen Standards für sehr hohe Datenraten bei kontaktlosen Smartcard Systemen nach ISO 14443. Das Ziel ist die Erreichung von Datenraten, die bedeutend über dem derzeitigen Maximum von 848 kbit/s liegen. Kontaktlose Smartcards sind eine Form von Chipkarten, auf die über ein hochfrequentes elektromagnetisches Feld zugegriffen werden kann. Die Kommunikation basiert auf induktiver Kopplung und benutzt eine Trägerfrequenz von 13.56 MHz. Für den Downlink (Karte zu Lesegerät) wird das Konzept der Lastmodulation verwendet. Wegen der engen Verwandtschaft zu RFID enthält der erste Teil dieser Arbeit einen Überblick über RFID Systeme. Der Stand der Technik bei kontaktlosen Smardcards wird präsentiert und Konzepte für hochratige Kommunikation werden vorgestellt. Im zweiten Kapitel werden die physikalischen, mathematischen und technischen Grundlagen von induktiv gekoppelten Übertragungssystemen beschrieben. Dies ist gefolgt von der Präsentation eines Matlab basierten Systemmodells im dritten Kapitel. Die Systemmodellierung beinhaltet eine Beschreibung der Übertragungskanäle für den Up- und Downlink mittels Übertragungsfunktionen und eine Auswertung der Abhängigkeiten vom Arbeitspunkt. Der Einfluss der Lastmodulation auf die Amplitude und Phase des Trägers wird berechnet. Die Konzeption der Test Plattform für sehr hohe Datenraten wird im vierten Kapitel präsentiert. Dies ist ein physischer Aufbau der die Generierung von verschiedenen Modulationsschemas erlaubt und zur Validierung von Sende- und Empfangskonzepten verwendet werden kann. Die analogen und digitalen Entwicklungen für die Test Plattform werden im fünften und sechsten Kapitel beschrieben. Das siebte Kapitel beinhaltet Ergebnisse von Messungen, die zur Validierung der Funktionalität der Test Plattform und zur Charakterisierung der Sendesignale von Up- und Downlink durchgeführt wurden. Im letzten Kapitel wird eine Zusammenfassung der erreichten Ergebnisse präsentiert und die nächsten Schritte im Entwicklungsprozess werden skizziert.

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Acknowledgment This work was created in the course of studies of Electronic Engineering at the University of Applied Sciences Kapfenberg. It was conducted in close cooperation with the company NXP Semiconductors in Gratkorn. First of all I want to thank Dr. Harald Witschnig for his great support throughout my time at NXP. As project leader of the VHD group he always was motivating and ready for discussion. Without him this work would not have been possible. I also want to thank Dr. Christian Netzberger who was my supervisor at the University. He always has time for his students and the skills and knowledge I learned from him were essential for this work. A big supporter of this work also was Dipl.Ing. Martin Gossar. He was a very helpful and cooperative colleague, whose company I appreciated much. At the design of the VHD amplifier I was supported by Dr. Michael Gebhart, whom I want to thank for his kind assistance. I further want to thank PDEng Massimo Ciacci for his useful feedback on an earlier version of this work. But above all I want to thank my mother. She always believed in me, supported me and without her, I would not be the one I am today.

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Contents Abstract

i

Kurzfassung

ii

Acknowledgment

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1. Introduction 1.1. Technological Overview . . . . . . . . . . . . 1.1.1. What is RFID? . . . . . . . . . . . . . 1.1.2. Classification of the Technology . . . . 1.1.3. Scope of this Work . . . . . . . . . . . 1.2. State of the Art . . . . . . . . . . . . . . . . . 1.2.1. The Working Principle . . . . . . . . . 1.2.2. Load Modulation with Subcarrier . . . 1.2.3. The Standard ISO 14443 . . . . . . . . 1.3. Very High Data Rates . . . . . . . . . . . . . 1.3.1. The Need for Very High Data Rates . 1.3.2. Proposal for Very High Data Rates . . 1.3.3. Challenges and Fields of Development 1.3.4. Work that has been done . . . . . . .

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2. Fundamentals 2.1. Physical Basics . . . . . . . . . . . 2.1.1. Magnetism . . . . . . . . . 2.1.2. Ampere’s Law . . . . . . . . 2.1.3. Faraday’s Law of Induction 2.1.4. Inductance . . . . . . . . . 2.2. Resonator Modeling . . . . . . . . 2.2.1. Resonator Circuits . . . . . 2.2.2. LTI System Modeling . . . 2.2.3. Quality Factor . . . . . . . 2.3. The Inductive Coupling System . . 2.3.1. Basic Building Blocks . . . 2.3.2. Inductive Loop Antennas . 2.3.3. Reader Topology . . . . . . 2.3.4. Transponder Topology . . .

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3. System Modeling 3.1. Theoretical Approach . . . . . . 3.1.1. Equivalent Circuit . . . . 3.1.2. Air Interface . . . . . . . 3.1.3. Numerical Evaluation . . 3.1.4. Resonator Parameters . . 3.1.5. Baseband Representation 3.2. Numerical Evaluation . . . . . . 3.2.1. Circuit Quantities . . . . 3.2.2. Reader Antenna . . . . . 3.2.3. Transponder Operation . 3.2.4. Energy Range . . . . . . . 3.2.5. Detuning Effects . . . . . 3.2.6. Transformed Impedance . 3.2.7. Load Modulation . . . . . 3.3. Conclusion . . . . . . . . . . . . . 3.3.1. Uplink . . . . . . . . . . . 3.3.2. Downlink . . . . . . . . .

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4. Conception of the Test Platform 4.1. Motivation . . . . . . . . . . . . . . . . . . 4.1.1. Verification of Theoretical Results 4.1.2. Validation of Transceiver Concepts 4.1.3. Development of Test Methods . . . 4.2. Requirements . . . . . . . . . . . . . . . . 4.2.1. System Requirements . . . . . . . 4.2.2. Carrier Generation . . . . . . . . . 4.2.3. Data Transmission . . . . . . . . . 4.2.4. Receiver Concept . . . . . . . . . . 4.2.5. User Interface . . . . . . . . . . . . 4.3. Implementation . . . . . . . . . . . . . . . 4.3.1. Overview . . . . . . . . . . . . . . 4.3.2. FPGA . . . . . . . . . . . . . . . . 4.3.3. Converters . . . . . . . . . . . . . . 4.3.4. Amplifier . . . . . . . . . . . . . . 4.3.5. Receiver . . . . . . . . . . . . . . . 4.3.6. Test Fixture . . . . . . . . . . . . . 4.3.7. Transponder . . . . . . . . . . . .

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5. Analog Development 5.1. Transmit Path . . . . . 5.1.1. Preamplifier . . . 5.1.2. Lowpass Filter . 5.1.3. Voltage Amplifier

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5.1.4. Current Amplifier . . . . 5.1.5. Transformer Output . . 5.2. Receive Path . . . . . . . . . . 5.2.1. Lowpass Filter . . . . . 5.2.2. Carrier Suppression . . 5.2.3. Level Adjustment . . . . 5.3. Data Converters . . . . . . . . 5.3.1. Analog to Digital . . . . 5.3.2. Digital to Analog . . . . 5.4. Final Result . . . . . . . . . . . 5.4.1. VHD Amplifier Board . 5.4.2. VHD Converter Board . 5.4.3. Complete Test Platform

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6. Digital Development 6.1. Methodology . . . . . . . . . . . . . . . 6.1.1. Design Approach . . . . . . . . . 6.1.2. Hardware Description Language . 6.1.3. Simulation . . . . . . . . . . . . . 6.1.4. Synthetisation . . . . . . . . . . 6.2. VHD IP Core . . . . . . . . . . . . . . . 6.2.1. User Logic Interface . . . . . . . 6.2.2. Transmission Unit . . . . . . . . 6.2.3. Receive and Bit Error Rate Unit 6.3. LCD IP Core . . . . . . . . . . . . . . . 6.3.1. LCD Hardware . . . . . . . . . . 6.3.2. User Logic Interface . . . . . . . 6.3.3. State Machine . . . . . . . . . . 6.4. Software . . . . . . . . . . . . . . . . . . 6.4.1. IP Core Drivers . . . . . . . . . . 6.4.2. Navigation Menu . . . . . . . . . 6.4.3. Serial Interface . . . . . . . . . . 6.4.4. Main Program . . . . . . . . . . 6.5. FPGA Configuration . . . . . . . . . . .

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7. System Characterization 7.1. Test Platform . . . . . . . . . . . 7.1.1. Transmit Path . . . . . . 7.1.2. Receive Path . . . . . . . 7.2. System Parameters . . . . . . . . 7.2.1. Reader Antenna . . . . . 7.2.2. Detuning by Amplifier . . 7.2.3. Detuning by Transponder 7.3. Data Transmission . . . . . . . .

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7.3.1. Uplink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.3.2. Downlink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 8. Recapitulation 8.1. System Modeling . . 8.2. Developed Hardware 8.3. Digital Design . . . . 8.4. Next Steps . . . . . .

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A. System Modeling 95 A.1. Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 A.2. Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 A.3. Simulation Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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1. Introduction 1.1. Technological Overview Contactless smartcard systems are based on a technology that is often subsumed under the term RFID. Because of this the first section of this work contains an overview on RFID and similar technologies that will be summarized by the term contactless technologies.

1.1.1. What is RFID? The acronym RFID stands for Radio Frequency Identification. It is a technology where a radio frequency field is used to interchange information between a reader device and a desirably small and simple transponder device. Such a transponder device can come in many different forms like flexible stickers called labels, solid capsules for implantation or plastic badges like key fobs. It can also be integrated in other objects like wristwatches, tickets, documents, mobile phones and many more. Some examples for transponder devices can be found in figure 1.1.

(a) Smart label

(b) Capsule

(c) Key fob

(d) Smartcard

(e) e-Passport

(f) Mobile phone

Figure 1.1.: Different forms of transponder devices

1

Short Historical Outline 1948

Earliest publication on a method of communication by means of reflected power by Stockmann [1]

1960s

First commercial application: Electronic Article Surveillance (EAS)

1980s

Applications in logistics, access control, animal identification

1990s

First RFID tag on a single integrated CMOS circuit

Present and Future Applications As can be seen from the historical outline above, the first commercial application was Electronic Article Surveillance (EAS). In this application the only purpose of a transponder is to indicate whether it is in the range of a reader device or not. Because of this such transponders are called 1-bit-transponders. They are very simple, cheap and today in widespread use. However, real identification is only possible if the transponder is capable of transferring more information to a reader device. A minimum requirement is a unique identification number consisting of several bytes. Transponders with such a functionality have become very common for applications in logistics, library management and animal identification. To some extent these are the same fields where bar code identification systems are in use. The advantage of RFID compared to optical identification systems is the increased flexibility and the better applicability in dirty environments. Some newer applications go beyond basic identification and demand security too. An example of such applications is the field of contactless smartcards. These cards are similar to classical credit cards or bank account cards but they need no mechanical interface to a reader device. This improves the usability and durability of such systems but it is also a possible source of security problems. Since the communication happens over the air interface, the data may not only be received by the correct reader device but also by an interceptor device. Because of this data encryption is a necessity for such applications. With the need for encryption the requirements on the functionality of a transponder rise. These increased requirements make it reasonable to separate these applications from basic RFID.

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A good example of the use of contactless smartcard technology can be found in the field of electronic government (e-Government). In new passports a transponder chip is integrated which makes it possible to store information in electronical form and access it over a contactless interface. This adds significantly to the fraud resistance of the document and makes it possible to store biometrical information on the chip. An application that emerged from contactless smartcards is called Near Field Communication (NFC). In this technology the functionality of a reader and a transponder are combined into one device. The typical use case for NFC is the integration of this readertransponder-device into a mobile phone. With such a mobile phone it is possible to read data from other transponder devices like smart labels, but it is also possible to exchange data with other NFC devices. Because of the short read range of below 10 cm it is ideal to perform secure transactions for electronic payment or electronic ticketing.1 Another advantage of the short read range is the natural way of enabling communication between two devices by simply holding them together. Beside the applications presented above there are many more like transponder timing at mass sports events, contactless sensor interfaces, car immobilizers2 , and electronic road pricing, to name just a few. For future applications there is still a big potential for growth, since RFID transponders can theoretically be integrated in every object. Such a development would finally lead to the so-called Internet of Things where information about a physical device can be obtained in a quick and easy way by just holding a reader device towards the object.

1.1.2. Classification of the Technology Because of the large diversity of RFID systems it is useful to classify these systems based on characteristic parameters. In the following such a classification will be presented based on read range, carrier frequency, coupling technique, and energy source [2]. Classification based on Read Range It is distinguished between close coupling where the read range is below 1 cm, remote coupling where the read range is up to 1 m and long range where the read range exceeds 1 m and can be up to 15 m.

1 2

Data encryption is nevertheless a mandatory functionality for secure transactions. An electronic device, integrated in the key of a car that prevents an unauthorized start of the engine.

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Classification based on Carrier Frequency RFID systems work in frequency regions from longwave up to microwave. Therefore they can be classified as low frequency (LF) systems which work in the range of 30 300 kHz, high frequency (HF) systems which work in the range of 3 - 30 MHz and ultra high frequency (UHF) systems which work in the range of 300 - 3000 MHz. The most common carrier frequencies are in the range of 9 - 135 kHz for LF, the ISM3 frequency 13.56 MHz for HF, the frequency range 865 - 868 MHz for UHF and the ISM frequency 2.45 GHz also for UHF. Classification based on Coupling The coupling mechanism of RFID systems can be based on electric coupling, magnetic coupling or electromagnetic coupling. Electric coupling has a very limited range and is therefore only relevant in close coupling systems. Magnetic coupling is the dominating technique in remote coupling systems which work either at LF or HF. Electromagnetic coupling appears when there is free wave propagation. This happens in the far field and is therefore used for long range systems which work in the UHF band. Classification based on Energy Source One big advantage of RFID systems is the transponder’s ability to draw energy from the field. If the whole energy which is needed by the transponder is obtained from the field, the transponder is called passive. However, this mechanism limits the read range of the device. Therefore passive transponders are only realistic in close and remote coupling systems. At long range systems the transponder has its own source of energy which is used to supply the integrated circuit. Because of this such systems are called active systems. The field of active systems can further be divided in systems where the generation of the carrier is performed solely by the reader and other systems where the transponder generates its own carrier. But strictly speaking the latter ones are no real RFID systems any more.

1.1.3. Scope of this Work This work focuses on inductively coupled transmission systems with a carrier frequency of 13.56 MHz. The basis should be the standard ISO 14443 [3], which describes the most common type of contactless smartcards called proximity cards.

3

Industrial scientific and medical: frequency bands that are typically used for unlicensed operation.

4

1.2. State of the Art In the following section a short overview on the state of the art of contactless smartcard systems is given.

1.2.1. The Working Principle Contactless smartcards according to ISO 14443 are coupled over the magnetic field. The antennas in use are called inductive loop antennas and are basically coils of wire. The reader device generates a magnetic field by supplying a current which flows through the reader antenna. This field is represented by magnetic field lines, depicted in figure 1.2.

Figure 1.2.: Coupling between a reader and a transponder antenna Coupling between the reader and the transponder antennas takes place when a part of the magnetic field lines of the reader antenna also pass through the transponder antenna. In this case a voltage gets induced in the transponder antenna which can be used to supply the transponder chip with energy. If the chip draws energy from the field in this way, a current will flow through the windings of the transponder antenna. As with the current in the reader antenna also the current in the transponder antenna causes a magnetic field to be built up. This new field in return induces a voltage in the reader antenna. And this is exactly the principle which is used to transfer data from the transponder to the reader. A switch on the transponder alternately changes the load of the transponder antenna between a normal amount and a state of higher loading. This changes the current that is drawn from the antenna and can be sensed at the reader as a change of antenna voltage. This way of communication is called load modulation.

5

1.2.2. Load Modulation with Subcarrier Above it was shown that a change of load at the transponder causes a change of voltage at the reader. But how exactly the reader voltage is modulated by the transponder is strongly dependent on the setup of the whole system and will be examined in more detail in chapter 3. For now the most intuitive case where a higher load at the transponder causes a drop in voltage at the reader should be assumed. Therefore the load modulation of the transponder will be visible at the reader as an Amplitude Shift Keying (ASK) modulation between two values. The change in voltage at the reader is however very little compared to the amplitude of the carrier. Because of this it is necessary to separate the data signal from the carrier before a demodulation can be performed. This separation is easier if the data signal is spectrally located at a place with enough distance to the carrier frequency fc . To achieve such a localization of the data signal in the spectrum a subcarrier is used. The subcarrier is generated by switching the load modulation switch at the transponder with a frequency fsub and a duty cycle of 50 % between on and off. As an effect of this two spectral components at the frequencies fc − fsub and fc + fsub will appear in the spectrum, which represent the lower and the upper subcarrier. The actual data signal is then modulated on these subcarriers. In figure 1.3 the resulting spectrum of such a modulation is depicted.

Figure 1.3.: The resulting spectrum at the reader

1.2.3. The Standard ISO 14443 The standard ISO 14443 defines two communication modes for the physical layer: type A and type B. Each type consists of modulation schemes for the uplink which is the direction from reader to transponder as well as for the downlink which is directed from transponder to reader.

6

Uplink For the uplink a form of ASK modulation is utilized. At type A it is a 100 % ASK modulation with modified Miller coded data. At type B it is a 10 % ASK modulation with non return to zero coded data. The resulting envelopes of the carrier for exemplary bit sequences are depicted in figures 1.4a and 1.4b.

(a) Type A

(b) Type B

Figure 1.4.: Signal envelopes for the uplink Downlink For the downlink a load modulation with use of a subcarrier is utilized. The subcarrier has a fixed frequency of fc /16 ≈ 848 kHz. At type A this subcarrier is modulated by on/off keying and Manchester coded data. At type B it is modulated by Binary Phase Shift Keying (BPSK) and non return to zero coded data. The envelopes of these modulations can be found in figures 1.5a and 1.5b.

(a) Type A

(b) Type B

Figure 1.5.: Signal envelopes for the downlink The bit rate for initialization is defined as fc /128 ≈ 106 kbit/s. The actual data transmission may then be performed at a higher bit rate of fc /64 ≈ 212 kbit/s, fc /32 ≈ 424 kbit/s or fc /16 ≈ 848 kbit/s. The last one represents a limit by this standard since the bit rate cannot be higher than the subcarrier frequency.

7

1.3. Very High Data Rates The term Very High Data Rates (VHD) refers to data rates that are considerably above today’s limit of 848 kbit/s. The following section gives and introduction on VHD.

1.3.1. The Need for Very High Data Rates At the beginning of RFID the amount of data that could be stored on a transponder was very low. Because of this the data transfer rate was of minor importance. Also with data rates of several kilobits per second, the transfer has been finished before a human being would have noticed that any time has passed anyway. But today there is the possibility to store much more information on a transponder device. This leads to new applications like e-Passports where biometrical information like a photo can be stored on the chip. For such an application at least several kilobytes of data are needed. With the basic data rate of 106 kbit/s the transfer of 50 kB takes approximately 3.9 seconds4 . This is perceived as a considerable delay and is therefore not acceptable for such an application. With today’s highest data rate of 848 kbit/s this transaction takes approximately 0.5 seconds, which is a passable value. Generally speaking a time which is not perceived as a delay is 0.3 seconds. The amount of data that can be transferred in this time with respect to different transfer rates is depicted in figure 1.6.

Amount of Data [kB]

Data Transfer in 0.3 Seconds 500 450 400 350 300 250 200 150 100 50 0 106

212

424

848

1695

3390

6780

13560

Data Rate [kbit/s]

Figure 1.6.: The amount of data that can be transferred in 0.3 seconds

If possible future applications require more than 50 kB while keeping the transaction time at a level that is not perceived as a delay, Very High Data Rates will be needed. 4

50 × 1024 × 8 bit ÷ 106000 bit/s = 3.864 s

8

1.3.2. Proposal for Very High Data Rates The subcommittee ISO/IEC JTC1/SC17 is responsible for standards concerning identification cards. Within this subcommittee there is a Working Group 8 (WG8) which is dedicated to the development of standards for contactless chipcards. In 2007 there was a proposal from NXP Semiconductors for a new concept for the physical layer of communication which allows much higher data rates. New Concept for the Uplink For the uplink (reader to transponder) a phase shift keying modulation on the carrier was proposed. The two parameters defining this modulation are the order of the PSK and the symbol rate. As an example an 8th order PSK (8-PSK) with a symbol rate of f c/4 ≈ 3390 kHz is depicted in figure 1.7. Time Domain 2.5

Constellation Diagram

4/fc

4/fc

4/fc

4/fc

0° 000

45° 001

90° 011

135° 010

1.5 011

2 1.5

1

Q

1 0.5 0

0

001

110

000

-0.5

-0.5 -1

-1 -1.5 0

010

0.5

111

100 101

200

400

600 800 Time [ns]

-1.5 -1.5

1000

-1

-0.5

0 I

0.5

1

1.5

Figure 1.7.: Time domain signal and constellation diagram of 8-PSK modulation The symbol codes in the example above follow a Gray coding scheme. This means that neighboring symbols in the constellation diagram represent bit codes that differ only in one bit. If a symbol error occurs, it is most likely that the false symbol is relatively close to the correct one in the constellation diagram. Therefore most symbol errors will only represent an error of one bit, which lowers the overall bit error rate.

9

New Concept for the Downlink For the downlink (transponder to reader) also a form of phase shift keying modulation was proposed. But because of the concept of load modulation it cannot be applied directly on the carrier but has to be applied on the subcarrier. The subcarrier is generated by a square wave signal that switches the load of the transponder between two states. A phase modulation of the subcarrier means therefore that this square wave signal is shifted in phase. As an example an 8th order PSK (8-PSK) with a subcarrier frequency of f c/16 ≈ 848 kHz and a symbol rate of the same value is shown in figure 1.8. Load Modulation 7

000

001

011

Symbols 100

8

6 5 16/fc

16/fc

16/fc

6

16/fc

4 4

3

000

110

001

111

011

101

010

100

2 2 1 0 0

1000

2000 3000 Time [ns]

0 0

4000

1000

2000 3000 Time [ns]

4000

5000

Figure 1.8.: Time domain signal and symbols of 8-PSK load modulation In the example above the subcarrier frequency and the symbol rate are equal. This means that there is one subcarrier period within one symbol. It would also be possible to choose a different value for the subcarrier frequency and another one for the symbol rate, as long as the symbol rate is lower or equal to the subcarrier frequency.5 The achievable data rate, however, depends only on the symbol rate. A higher subcarrier frequency would result in a shift of the data signal farther away from the carrier. This would mean a higher damping caused by the bandpass characteristic of the channel. Therefore it is most likely not advantageous to choose the subcarrier frequency higher than necessary.

5

This is the case in the current version of ISO 14443, where the subcarrier frequency is f c/16 and the symbol rate can be set to fc /128, fc /64, fc /32 or fc /16.

10

Achievable Data Rates The data rate that is achieved by a specific form of PSK modulation can be calculated by multiplying the symbol rate by the number of bits per symbol. A summary of the achievable data rates with various modulation schemes can be found in table 1.1. PSK Order Bits/Symbol Symbol Rate f c/128 ≈ 106 kHz f c/64 ≈ 212 kHz f c/32 ≈ 424 kHz f c/16 ≈ 848 kHz f c/8 = 1695 kHz f c/4 = 3390 kHz f c/2 = 6780 kHz f c = 13.56 MHz

2 1

4 2

8 3

16 4

32 5

64 6

128 7

256 8

742 1483 2966 5933 11865 23730 47460 94920

848 1695 3390 6780 13560 27120 54240 108480

Resulting Data Rate [kbit/s] 106 212 424 848 1695 3390 6780 13560

212 424 848 1695 3390 6780 13560 27120

318 636 1271 2543 5085 10170 20340 40680

424 848 1695 3390 6780 13560 27120 54240

530 1059 2119 4238 8475 16950 33900 67800

636 1271 2543 5085 10170 20340 40680 81360

Table 1.1.: Data rates for various modulation schemes (rounded)

One major concern targeting standardization is the selection of one modulation scheme out of table 1.1 that is best suited for the real physical setup.

1.3.3. Challenges and Fields of Development

Quality Factor versus Bandwidth The main factor that limits the data rate of an inductively coupled transmission system is the bandpass behavior of the inductive loop antenna. Such an antenna can be described by a resonance frequency f0 and a quality factor Q. For a common reader device f0 will be tuned to 13.56 MHz and Q will be set to approximately 35. The value of 35 results from a compromise between energy efficiency and bandwidth. From the energy point of view it is desirable to have a high quality factor since it is proportional to the superelevation of the current through the antenna windings at resonance frequency. From the bandwidth point of view it is desirable to have a low quality factor since it is also inverse proportional to the −3 dB bandwidth of the bandpass and directly proportional to the time constant of the step response. A comparison between low and high quality factor in frequency and time domain is shown in figure 1.9.

11

Frequency Responses

Pulse Shapes

40 Q = 35 Q = 10 30

80 Signals

Magnitude

Q = 35 Q = 10

100

387kHz 20

60 40

10 20

1356kHz 0

13

13.5 f [MHz]

14

0 0

14.5

1000

2000 3000 time [ns]

4000

5000

Figure 1.9.: Frequency responses and pulse shapes of different channels The quality factor can be used to predict the transient behavior of the system. In an idealized second order system the response to a sinusoidal input of frequency fc that is switched from one amplitude to another will show an exponential behavior with a time constant in a way that the steady state is reached practically in Q carrier periods.6 Applied on data transmission this means that if the symbol duration is longer than Q carrier periods, past symbols will have no influence on future symbols. Otherwise if the symbol duration gets shorter than Q carrier periods, there will be an effect on future symbols. This effect is known as intersymbol interference (ISI) and complicates the detection of the correct symbols. From the consideration above it can be concluded that ISI will occur if the symbol rate gets higher than fc /Q which is approximately 387 kHz for Q = 35. Basically there are two ways to prevent ISI. The first one is to set the symbol rate to a low value and leave the quality factor at the current value of 35. The problem with this option is that Very High Data Rates will most likely require a higher symbol rate. The second option is to lower the quality factor. This, however, is not wanted either since it would lead to a lower efficiency of the reader device. The conclusion is that ISI has to be accepted and methods of digital signal processing have to be applied to detect the correct symbols, despite of ISI.

6

After a time t = Q/fc the step response has reached 1 − e−π of the final value which is approximately 95.7 %.

12

Further Topics Beside the development of a new concept of the physical layer there are also other topics that have to be covered. It has to be investigated how to implement Very High Data Rate communications while retaining compatibility with present systems. One option is to expand the current standard ISO 14443 in a way that it is capable for this new type of communication. But the drawback of this option is that the initialization part of the communication would still have to be performed at the slow transmission rate of approximately 106 kbit/s. The other option is to develop a completely new standard for Very High Data Rates. In this case new reader devices would have to be capable of both standards and the initialization procedure would have to be made in a way that both old and new cards can be handled by such a reader. Another topic of great importance is the actual implementation in hardware. It is desirable to keep the signal processing on the transponder integrated circuit (IC) as simple as possible since this part is very cost sensitive. If possible, most of the necessary signal processing should be located at the reader device. But also the analog and mixed signal part of the transponder IC needs to be adapted for the use of Very High Data Rates. A critical parameter for this design will be the energy consumption, since higher clock rates lead to increased current consumption. Finally also the memory technology has to be improved in storage capacity and access time to make Very High Data Rates practical for a real world application.

1.3.4. Work that has been done In the past several diploma theses were written at NXP Semiconductors Gratkorn concerning Very High Data Rates [4] [5] [6] [7] [8] [9]. In these theses concepts for the up- and downlink were investigated with the use of simulations and physical implementations. Furthermore, a demonstration platform was built which can be used to visualize a downlink data transmission of 6.78 Mbit/s [10]. The modulation scheme used at this demonstrator is a 2-PSK with a symbol rate of f c/2 = 6780 kHz and a subcarrier frequency of the same value.

13

2. Fundamentals 2.1. Physical Basics In the effort to describe inductively coupled systems it is useful to first review the physical basics and introduce the necessary quantities.

2.1.1. Magnetism Magnetism is a physical phenomenon that is caused by the motion of charge carriers. An example of moving charge carriers is the flow of electrons through a wire. This flow is called current and is measured in ampere.

I=

dQ dt

[A]

(2.1)

Current flowing through a wire produces a magnetic field around it that can be represented by magnetic field lines. These field lines have no real physical meaning, they only describe the effect that a magnetic field has on objects within it.

Figure 2.1.: A magnetic field, represented by field lines around a wire

14

Magnetic Quantities To describe a magnetic field quantitatively it is necessary to introduce some magnetic quantities. The first one is the magnetic field strength H that is measured in ampere per meter. It is a material independent, vectorial quantity, which means that for every coordinate in space there is a direction and a magnitude of the magnetic field. The distribution of magnetic field lines in space depends on the material that occupies this space. In some materials the field lines are much closer together than in free space. These materials are called highly permeable. To measure the density of field lines it is necessary to introduce the magnetic flux density B that is measured in volt seconds per square meter or tesla. As H also B is a vectorial quantity that has a direction and a magnitude at every coordinate in space. The relation between B and H is called permeability µ. It is composed of the magnetic constant µ0 which represents the permeability of free space and a factor called relative permeability µr .

B = µH

(2.2)

µ = µ0 µr

(2.3)

µ0 = 4π10−7

Vs Am

(2.4)

The third magnetic quantity that is introduced is the magnetic flux Φ. It is measured in volt seconds or weber and indicates how many field lines pass through a finite region of space. It is obtained from the magnetic flux density by integration over the area of consideration. ZZ B dA

Φ=

(2.5)

A

A summary of the introduced magnetic quantities and their counterparts in the electric field can be found in table 2.1 [11]. Magnetic Field Symbol H B Φ

Unit A/m V s/m2 Vs

Electric Field

Name Magnetic field strength Magnetic flux density Magnetic flux

Symbol E D Ψ

Unit V /m As/m2 As

Name Electric field strength Electric flux density Electric flux

Table 2.1.: Quantities of magnetic and electric fields

15

2.1.2. Ampere’s Law By Ampere’s law it is possible to connect the magnetic field strength H with its cause, the electric current, represented by the current density J. ZZ

I

J dA

H dr =

(2.6)

A

C

To make this law more intuitive it should be visualized by an example from the beginning of this chapter. If current flows through a wire, a magnetic field will form around it as depicted in figure 2.2. If the magnetic field strength is summed up over any arbitrary path around the wire (path integral over C), this is equal to the amount of current flowing through the region of space enclosed by that path (surface integral over A).

Figure 2.2.: Visualization of Ampere’s Law If equation 2.6 is evaluated for a specific physical setup, a formula for the calculation of the magnetic field strength H, depending on the current I and the position in space can be obtained. Two exemplary setups and their formulas are shown in figure 2.3 [2].

H=

IN r2 H= p 2 (r2 + x2 )3

I 2πr

Figure 2.3.: Exemplary setups for field strength calculation

16

2.1.3. Faraday’s Law of Induction Faraday’s law of induction describes the generation of an electric field under the influence of an alternating magnetic field. I

∂ E dr = − ∂t C

ZZ B dA

(2.7)

A

A visualization of this law can be found in figure 2.4. If a loop of wire is under the influence of an alternating magnetic field, a voltage will appear across the ends of the wire. According to Faraday’s law this voltage (represented as an integration of the electric field around the wire) is equal to the rate of change of the magnetic flux density through the inner area of this wire loop, but with a negative prefix.

∂ B ∂t

Figure 2.4.: Visualization of Faraday’s Law of Induction If we restrict the setup to the special case of the last example, Faraday’s law of induction can also be expressed in a simpler form, which is stated in equation 2.8.

Uinduced = −N

dΦ dt

(2.8)

This equation describes the voltage induced into a coil consisting of N loops of wire, caused by an alternating magnetic flux Φ through the windings. Lenz’s Law The negative prefix in the equations results from the law of conservation of energy and is also known as Lenz’s law:

"The induced current in a coil is always directed against its cause."

17

2.1.4. Inductance The inductance is a property of an electric circuit that describes the relation between the magnetic flux Φ and the current I. Self Inductance The self inductance L is defined as the ratio of the overall magnetic flux through the area of a loop, referred to the current in the loop. If the loop has more than one winding, each winding adds to the overall flux. Therefore a new quantity called flux linkage Ψ is introduced which is the flux Φ times the number of windings N 1 .

L=

Ψ I

with Ψ = N Φ

(2.9)

Figure 2.5.: Self Inductance of a wire loop The ratio of the voltage across the loop referred to the current in the loop is the impedance and can be calculated as XL = jωL. Since this impedance is positive and imaginary, the current in the loop will be delayed by 90◦ with respect to the voltage. Mutual Inductance The mutual inductance M is used to describe the coupling between two loops of wire that are in the vicinity of each other. It is defined as the ratio of the magnetic flux through the area of the second loop, referred the current in the first loop. As can be seen in equation 2.10 it can also be defined the other way around which leads to the same result.

M21 =

1

ΨA2 (I1 ) I1

M12 =

ΨA1 (I2 ) I2

M = M21 = M12

(2.10)

The flux linkage Ψ should not be confused with the electric flux Ψ which was introduced on page 15.

18

Figure 2.6.: Mutual Inductance of two loops of wire Coupling Factor Because of the dependence of the mutual inductance on the physical dimensions of the circuit, it is not suited for a generalized comparison. Because of this the coupling factor is introduced, which is defined according to equation 2.11. Its value can range from zero to one and it is scale invariant with respect to the coil’s inductances.

k=√

M L1 L2

(2.11)

Induced Voltage To finalize this section it will be shown how the mutual inductance can be used to calculate the induced voltage in one coil, caused by an other coil. By Faraday’s law of induction the induced voltage in the second coil can be calculated as follows.

u2 =

dΨA2 dt

(2.12)

From the definition of the mutual inductance it can be derived that ΨA2 = M i1 . Furthermore if sinusoidal signals are assumed the derivation in equation 2.12 can be replaced by a multiplication by jω. This leads to the following equation.

u2 = jωM i1

(2.13)

From this it can be seen that the mutual inductance can be used to calculate a complex impedance XM = jωM , like it is the case with the self inductance XL = jωL. The only difference is that the voltages and currents now refer to different coils.

19

2.2. Resonator Modeling The resonators that are comprised by the inductive loop antennas are key elements when it comes to Very High Data Rates. Because of this a mathematical description of resonators will be presented in the following.

2.2.1. Resonator Circuits Basically there are two types of resonator circuits: serial and parallel (figure 2.7). Both consist of a resistor, a capacitor and an inductor. The difference between these two types is the connection of the elements, either in serial or in parallel. The mathematical description, however, is equivalent for both types. Furthermore, it is also equivalent to mechanical systems like spring-mass-pendula. Generally speaking every system where energy is converted periodically between two different forms can be described by the same mathematical formula which is a second order differential equation. In the following this equation should be derived out of the serial resonator circuit depicted in figure 2.7a.

(a) Serial resonator

(b) Parallel resonator

Figure 2.7.: Basic resonator circuits As a starting point the mesh equation according to Kirchhoff’s voltage law is set up. 1 u = Ri + C

Z i dt + L

di dt

(2.14)

If another derivation is performed and the equation is divided by L, it becomes an ordinary second order differential equation with constant coefficients. 1 1 du d2 i R di + + i= 2 dt L dt LC L dt

20

(2.15)

To make the equation more general two new variables are introduced: the attenuation α and the natural angular frequency ω0 . Furthermore the right side of the equation is substituted by a function r(t) that is called forcing function. d2 i di R 1 1 du + 2α + ω02 i = r(t) with α = , ω0 = √ , r(t) = 2 dt dt 2L L dt LC

(2.16)

The solution for the current i can be found as a superposition of the general solution of the homogeneous equation ih where r(t) = 0 and a particular solution ip of the nonhomogeneous equation where r(t) 6= 0. The first one describes the transient behavior of the system and the latter represents the steady state [12].

i = ih + ip

(2.17)

First ih is found with the assumption that ih = eλt . This exponential and its derivatives are inserted into the homogeneous equation which leads to the characteristic equation.

λ2 + 2αλ + ω02 = 0

(2.18)

The solution of this characteristic equation has the following form.

λ = −α ±

q α2 − ω02

(2.19)

Depending on the value of the variables under the square root (positive, zero or negative), there are three possibilities of the solution of the characteristic equation.

1. λ = −α ±

q

α2 − ω02

(2.20)

2. λ = −α

(2.21)

q 3. λ = −α ± j ω02 − α2

(2.22)

Depending on these three possible solutions of the characteristic equation, there are three possible solutions for the homogeneous equation.

21

1. ih = C1 eλ1 t + C2 eλ2 t 2. ih = (C1 + C2 t)e

(2.23)

−αt

(2.24)

3. ih = (C1 cos ωd t + C2 sin ωd t) e−αt

q with ωd = ω02 − α2

(2.25)

The damping ratio ζ = α/ω0 is a useful variable that helps discriminate the three cases above. Depending on the value of ζ the transient behavior of the system can be described as overdamped (ζ > 1, 1st case), critical damped (ζ = 1, 2nd case) and underdamped (ζ < 1, 3rd case). For the description of antenna resonators the relevant case is the third one since the damping ratio of these resonators is far below one. In this case the transient behavior is an exponentially decaying sine wave of frequency ωd , which is the natural damped angular frequency of the system. After a general solution of the homogeneous equation has been found, a particular solution ip of the non-homogeneous equation must be found. This particular solution represents the steady state of the system. If the forcing function is a harmonic oscillation, the steady state will also be a harmonic oscillation of the same frequency but with different amplitude and phase. Because of this the following starting point is chosen.

ip = A cos ωt + B sin ωt

(2.26)

This formula and its derivatives are inserted into the non-homogeneous equation and the constants A and B are determined by a comparison of coefficients. Then the two solutions ih and ip are combined and the constants C1 and C2 are determined with the use of boundary conditions. In our example these conditions are that the current and its first derivative are zero at time zero. Finally the general solution for the underdamped case can be written as follows.

i = ih + ip = Ah sin (ωd t + ϕh ) e−αt + Ap sin (ωt + ϕp )

(2.27)

A plot of the resulting time functions for the component values shown below can be found in figure 2.8 on page 23. Note the slight overshoot of the resulting time function compared to the steady state that is caused by the difference between ω and ωd .

Setup: R = 1 Ω , C = 100 pF , L = 1 µH , ω = 2 π 15 MHz Natural Frequencies: ω0 = 2 π 15.915 MHz , ωd = 2 π 15.896 MHz

22

1

0.5 ih( t) ip( t)

0

i( t) − 0.5

−1

0

100

200

300

400

t ns

Figure 2.8.: Time functions of ih , ip and i

2.2.2. LTI System Modeling Above a resonator circuit has been described in terms of solving its underlying differential equation. The purpose behind that was to gain knowledge about fundamental system parameters like the attenuation α, the natural angular frequency ω0 or the natural damped angular frequency ωd . The mathematical description in time domain is, however, complicated. A more practical approach is the description in frequency domain by the use of transfer functions. This method is applicable to linear, time invariant (LTI) systems. Linearity means that the properties of superposition and scaling are applicable. Time invariance means that a time shift of the input function will result in a time shift of the output function. A mathematical formulation of these properties for a system operator H can be found in equations 2.28 and 2.29.

Linearity: H {αx1 (t) + βx2 (t)} = αy1 (t) + βy2 (t) Time Invariance: H {x(t + τ )} = y(t + τ )

(2.28) (2.29)

To find the transfer function of the serial resonator discussed above, the starting point is again the differential equation from the previous section. d2 i di 1 du + 2α + ω02 i = dt2 dt L dt

(2.30)

But now the Laplace transform is applied to it. This results in the following algebraic equation including the complex variable s.

23

s2 i + 2αsi + ω02 i =

1 su L

(2.31)

Note that the symbols of the current and voltage have now an overline attached. This should express that they are not functions of time any more, but functions of s since they are the Laplace transformed equivalents of the time domain functions. The transfer function H(s) of a system is defined as the ratio of the Laplace transforms of its output quantity to its input quantity. Therefore the transfer function of the serial resonator can be derived by rearranging equation 2.31 to express the ratio of i over u.

H(s) =

1 s 2 L s + 2αs + ω02

(2.32)

In some cases it is useful to bring the transfer function to a form where s is normalized to ω0 . This leads to equation 2.33, where the main fractional is unitless and the unit of the whole transfer function is located in gn which is the normalized gain factor. In the example of the serial resonator, gn is a transconductance with the unit Ω−1 .

H(s) = gn

1+

s ω0 2ζ ωs0

+

s2 ω02

with gn =

1 ω0 L

(2.33)

Poles and Zeros The transfer function from equation 2.32 is a fractional polynomial of the complex variable s. In general such a polynomial can be described by its poles and zeros. To find these poles and zeros, the denominator and numerator are set equal to zero and the resulting equations are solved for s. With these results the transfer function can be brought to its factorized form, which is shown in equation 2.34.

H(s) =

1 s L (s − p) (s − p∗ )

(2.34)

It has one zero at s = 0 and two complex conjugate poles at the following positions.

p = σ + jωp

)

p∗ = σ − jωp

24

σ = −α q ωp = ω02 − α2

(2.35)

If these pole and zero locations are inserted in a diagram of the complex s-plane, this is known as a pole zero map. Poles are marked with a cross, zeros with a circle. In figure 2.9a such a map is shown for the example of the serial resonator, including the geometric relations of the pole locations with the system parameters α, ωd and ω0 . Pole Zero Map

8

Magnitude |H(jω)| [Ω-1]

x 10 1 0.5

ω0

ω

α

0 ωd

-0.5

ω

0

-1 -10

-5

0.05 0 0

10

20

30

20

30

f [MHz] Phase ∠ H(jω) [deg]

ωp

d

0.1

0

σ

5 x 10

100 0 -100 0

6

10 f [MHz]

(a) Pole zero map

(b) Frequency response

Figure 2.9.: Pole zero map and frequency response of serial resonator example Frequency Response An important advantage of transfer functions is the ability of calculating a frequency response of the system. This means the reaction of the system in terms of magnitude and phase as a function of frequency. To calculate this frequency response the complex variable s is replaced by jω and the absolute value, respectively the argument of the resulting term is determined. If this is done for equation 2.32 it leads to the formulas below. A plot of the frequency response can be found in figure 2.9b.

|H(jω)| =

1 q L

ω02



ω 2

ω2

 arg {H(jω)} = arctan 2

+ (2αω)

ω02 − ω 2 2αω

 (2.36)

From the equations above, the reaction of the system at resonance frequency ω0 can be predicted. It is easy to see that for ω = ω0 the phase gets zero. If the formula of the magnitude is examined, it can also be shown that for ω = ω0 the amplitude reaches a maximum. Note that this is only valid for a bandpass configuration. In a lowpass configuration the maximum amplitude will bepat a frequency that is a little bit lower than the resonance frequency, namely at ω = ω02 − 2α2 .

25

2.2.3. Quality Factor The quality factor is a physical property that relates the energy stored in a system to the loss of energy during one period of oscillation. It is defined in the following way:

Q=ω

Energy stored in System E = 2π P Energy Loss per Period

(2.37)

From this definition it can be seen that the quality factor can be used as a measure of efficiency. The higher it is, the less energy gets wasted. The disadvantage of high quality factor systems is that they are relatively inert, therefore they will react slowly to changes. Also detuning effects are an issue with high quality factor systems. In the following it will be shown how the quality factor of a resonator circuit can be calculated. For this purpose two quantities are needed: the energy and the power loss. The energy of a simple resonator circuit, like it was presented in the previous section, is alternately stored in the inductor and the capacitor. Therefore it can be calculated by the following formulas.

1 EL = Li2L 2

1 EC = Cu2C 2

(2.38)

For ease of calculation it is reasonable to consider a point in time where the whole energy is stored either in the inductor or the capacitor. Therefore the quantities ˆiL and u ˆC are introduced that represent the maximum current through the inductor or the maximum voltage across the capacitor at one cycle of oscillation. 1 1 2 E = LiˆL = C uˆC 2 2 2

(2.39)

The power loss happens in the resistor and can be calculated as follows.

P =

2 Ueff 1 uˆR 2 = R 2 R

1 2 2 P = Ieff R = iˆR R 2

(2.40)

If these formulas are inserted in the definition of the quality factor from equation 2.37, a formula for the quality factor can be derived that depends only on component values.

26

Especially for the simple resonator circuits discussed above, this leads to the following equations for the quality factor at resonance frequency.

r |XL | |XC | 1 L Q= = = R R R C r R R C Q= = =R |XL | |XC | L

for a serial resonator

(2.41)

for a parallel resonator

(2.42)

Another definition of the quality factor is located in the frequency domain. It is defined as the center frequency of a resonator over its −3 dB bandwidth.

Q=

f0 B

(2.43)

This definition is equivalent to the previous one if the system under consideration is a two pole system with low damping. Since antenna resonators are such systems, it can be used interchangeably with the previous definition. An advantage of the latter is that it connects the efficiency of the system with properties in the frequency domain. Furthermore the quality factor relates to the damping ratio in the following way [13].

Q=

1 2ζ

(2.44)

Because of this the quality factor can be used directly in the transfer function from equation 2.33 on page 24 like it is shown below.

H(s) = gn

1+

s ω0 1 s Q ω0

+

with gn =

s2 ω02

1 ω0 L

(2.45)

The magnitude of this function can be calculated as follows.

|H(jω)| = gn r

ω ω0

1−

ω2 ω02

2

+



1 ω Q ω0

2

(2.46)

For ω = ω0 it reduces to |H(jω0 )| = gn Q, which shows that Q defines the superelevation of magnitude at resonance frequency.

27

2.3. The Inductive Coupling System In the following the basics of inductively coupled transmission systems will be presented.

2.3.1. Basic Building Blocks An inductively coupled transmission system consists of the building blocks that are depicted in figure 2.10. It can be divided in Reader, Transponder and Antennas. In the following each of these elements will be described.

Figure 2.10.: Basic building blocks of inductively coupled transmission systems

2.3.2. Inductive Loop Antennas Inductive Loop Antennas are basically coils of wire. Because of this the dominating part in the equivalent circuit of such an antenna is an inductance (La ). But as with every physical device there are also parasitics and non-idealities. There is the ohmic resistance of the coil which is represented as a serial resistor (Ra ) and there is a parasitic capacitance which is represented by a parallel capacitor (Ca ). From this equivalent circuit, which can be seen in figure 2.11, it can be concluded that inductive loop antennas on their own are already a form of resonator.

Figure 2.11.: The equivalent circuit of an inductive loop antenna

28

The component values in the equivalent circuit depend solely on the geometric implementation of the antenna. Within this work two specific antenna implementations are used. For a reader device the round antenna defined in the test setup of ISO 10373-6 [14] is used. For the transponder device an antenna with an outline called ID-1, according to ISO 7810 [15] is used. In the following these two antennas are called ISO and ID1. A summary of the characteristics of these two antennas can be found in table 2.2.

Shape Dimensions Windings La Ra Ca fSelf Resonance QSelf Resonance Q13.56 MHz

ISO round ∅ 150 mm 1 477 nH 274 mΩ 25 pF 46 MHz 503 148

ID1 rectangular 72 × 42 mm 4 2.298 µH 1.286 Ω 5.9 pF 43.2 MHz 485 152

Table 2.2.: Characteristics of the antennas in use Measurement of Antenna Parameters The values in table 2.2 were obtained by measurements with a network analyzer and further calculations. The used method [16] will be described in the following. First the network analyzer has to be calibrated. After this the antenna is connected to one port of the instrument and the analyzer is set to measure the reflection parameter S11 . For the calculation of the antenna parameters the measurement should span from a low frequency (1 MHz) to the estimated self resonance frequency2 (40 to 50 MHz). At low frequency the capacitance can be neglected and the dominating parts are the ohmic resistance (R1M ) and the inductance (L1M ). These values can be extracted out of the measured impedance. At self resonance frequency (fSR ) the dominating part of the antenna is a parallel resonator. From the value of the self resonance frequency the parallel capacitance can be calculated and from the measured impedance the parallel damping resistance can be extracted. The values of the inductance and the capacitance don’t change much over frequency and so the obtained values can be used in the equivalent circuit. The ohmic resistance however does change over frequency. Because of this it must be calculated as a sum of the ohmic resistance at low frequency (R1M ) and an additional part that is mainly caused by the skin effect at higher frequencies. The calculated resistance is then valid at the operation frequency (fOP ) of 13.56 MHz. A summary of the calculations can be found in equation group 2.47 on page 30. 2

the frequency where the imaginary part of the impedance becomes zero

29

La = L1M

Ca =

(2πfOP La )2 Ra = R1M + q fSR fOP RSR

1 (2πfSR )2 La

(2.47)

2.3.3. Reader Topology In the previous section the properties of inductive loop antennas were presented. It was shown that their equivalent circuit is a resonator with a very high quality factor and a resonance frequency between 40 and 50 MHz. For the operation as a reader antenna these two properties need to be adapted to a quality factor of around 35 and a resonance frequency of 13.56 MHz. The quality factor can be lowered by adding a serial resistor to the antenna. The resonance frequency can be lowered by adding a parallel capacitor. The effect of this adaption to the frequency response can be seen in figure 2.12. Antenna Frequency Response 600 Normalized Magnitude

Add resonance capacitor 500 400 300

Add damping resistor

200 100 0 10

20

30 40 f [MHz]

50

60

Figure 2.12.: Adaption of antenna quality factor and resonance frequency Beside the quality factor and the resonance frequency there is another property that has to be considered. If an ISO antenna is adapted in the way described above, it has an input impedance of around 1.4 kΩ at operation frequency. If the antenna is connected over a transmission line with a characteristic impedance of 50 Ω, this will lead to a high reflection factor and low power transfer. But also, if the antenna is connected directly to an amplifier, the antenna resistance will be too high for an optimal operation point. Because of this impedance matching is needed.

30

Basically there are four types of passive impedance matching networks [17]. They are called L-section, reversed L-section, Π-section and T-section. Because of practical considerations the only components used in these networks are capacitors. Figure 2.13 contains an overview of the four types.

(a) L-section

(c) Π-section

(b) reversed L-section

(d) T-section

Figure 2.13.: Different forms of impedance matching networks For impedance matching of the reader antenna the favorable network is the reversed L-section in figure 2.13b. It only consists of two components and capacitor C2 can also be used to adjust the antenna’s resonance frequency. The final reader topology is depicted in figure 2.14. In a real implementation the capacitor C2 will be trimable to allow the adjustment of the resonance frequency. The damping resistor Rd will consist of several general purpose resistors in parallel because of the large amount of current that flows through it. The dimensioning of component values can be performed by approximative formulas that are depicted in equations 2.48 - 2.50 [16]3 .

Figure 2.14.: Reader antenna with matching network and damping resistor

ωLa − Ra Q 1 (ωLa )2 C1 = p with Rp = Ra + Rd ω Rmatch Rp 1 C2 = 2 − Ca − C1 ω La

Rd =

3

The dimensioning according to ISO 10373-6 is: C1 = 47 pF, C2 = 215 − 242 pF, Rd = 0.94 Ω

31

(2.48) (2.49) (2.50)

Resonator Type The resonator that is formed out of the reader antenna is not a simple serial or parallel one but it is a mixed type for the following reason. The input of the circuit is a voltage and the output is a current4 . This is characteristic for a serial resonator, like it was depicted on page 20. But the problem with a serial resonator is that there is no superelevation of current but of voltage. Because of this the resonance capacitor must be connected in parallel with the antenna to ensure that at resonance frequency the current through the antenna is a multiple of the input current.

2.3.4. Transponder Topology At the transponder there is basically the same antenna as at the reader except that in most cases it is smaller and has a higher inductance. For the setting of resonance frequency there is again a capacitance in parallel with the antenna. It is composed of the parasitic capacitance of the transponder IC and an additional capacitor (also integrated) that defines the resonance frequency. This resonance frequency is not exactly tuned to 13.56 MHz, but it can be up to 16 MHz. The large span is caused by tolerances of the integrated capacitor, but it is also designed to be slightly above 13.56 MHz.

Figure 2.15.: Principle schematic of a transponder circuit The first part on this IC is a full bridge rectifier that converts the sinusoidal voltage from the antenna to a DC voltage which is needed to supply the chip. The limiter, represented by a Zener diode, is an important part in this context. It is responsible for limiting the supply voltage to a constant level. If the voltage gets too high, the limiter will become less resistive and lowers the antenna’s quality factor. This in return lowers the induced voltage. Without a limiter this voltage could easily reach levels that would destroy the IC. Beside the limiter there is another part on the transponder that is used to lower the quality factor, namely the load modulation switch, represented by a MOSFET transistor. Finally there is the data processing circuit, modeled by an ohmic resistance.

4

the current through the antenna coil which generates the magnetic field

32

3. System Modeling 3.1. Theoretical Approach The development of Very High Data Rates requires a deeper understanding of the system and a model of the transmission channel. In the following the theoretical approach to this problem will be presented.

3.1.1. Equivalent Circuit The equivalent circuit of the system is composed of the reader and the transponder circuit from chapter 2, with a few modifications and can be seen in figure 3.1. At the reader side an amplifier is added as a voltage source u0 with an ohmic source resistance RS . At the transponder side the whole IC is modeled as a variable resistance RT . When the system is evaluated a value for RT has to be calculated in a way that the transponder voltage reaches a predefined level. In this way the functionality of the limiter is simulated. The load modulation can also be modeled as a change of the transponder resistance RT .

Rs

C1

Rd

Ra1

Ra2 k

u0

C2

Ca1

La1

La2

Ca2

Ct

Rt

Figure 3.1.: Equivalent circuit for system modeling The goal of the system modeling that will be presented in the following is the extraction of a channel transfer function from reader to transponder out of the circuit in figure 3.1. Since this circuit is linear for a specific operation point it would be possible to derive this transfer function in an analytical way. But because of the high number of distinct energy storing elements in the circuit such an approach would lead to very long terms and a high order transfer function that is hard to handle. Because of this an other approach will be presented where the frequency response of the system is calculated numerically and the channel parameters are extracted out of this frequency response.

33

3.1.2. Air Interface Since the equivalent circuit of figure 3.1 is linear for a specific operation point, it can be evaluated by methods of classical circuit analysis. The only part which is unfamiliar for this type of evaluation is the air interface. In the following a description of this interface based on a transformed impedance will be presented. A simple example using two circuits that are coupled over inductors will be examined to derive this description. As can be seen in figure 3.2 the first circuit has a voltage source uS and a source impedance ZS . The second circuit has a load impedance ZL . Because of the coupling between the circuits a voltage is induced in the second one that depends on the current in the first one. In return a voltage is induced also in the first circuit that depends on the current in the second one. 1

2

S

S

1

i1

L

2

2

i2

1

Figure 3.2.: Two circuits, coupled over inductors To describe the two circuits the mesh equations according to Kirchhoff’s voltage law are set up. With two abbreviations this leads to the following equations.

Z1 = ZS + jωL1 Z2 = ZL + jωL2

)

1. uS = Z1 i1 − jωM i2 2. 0 = Z2 i2 − jωM i1

When the second mesh equation is rearranged after i2 and inserted into the first one the following two equations are the result.

jωM i2 = i1 Z2

  ω2M 2 uS = i1 Z1 + Z2

(3.1)

From the last one it can be seen that the first circuit has an impedance Z1 plus an additional part that is caused by the induced voltage from the second circuit. The additional impedance is called transformed impedance Zt and represents the impedance

34

of the second circuit, transformed into the first one. It can be written as the complex conjugate of the second circuit’s impedance Z2 , multiplied with a scaling factor.

Zt =

ω2M 2 ∗ ω2M 2 = Z2 Z2 |Z2 |2

(3.2)

3.1.3. Numerical Evaluation To evaluate the system numerically first the impedances are calculated, beginning at the transponder side. After that the currents are calculated, beginning at the reader side. The voltages can finally be calculated out of the currents and impedances.

8

7

6

5

0

4

d

s

1

d

1

1

a1

0

a2 a1

2

c

2

a2

a1

t a2

3

2

Figure 3.3.: Definition of system impedances and currents % impedances Z1 = 1 / ( j * w *( Ct + Ca2 ) + 1/ Rt ); Z2 = j * w * La2 + Ra2 + Z1 ; Z3 = w ^2 * M ^2 / Z2 ; Z4 = Ra1 + j * w * La1 + Z3 ; Z5 = 1 / ( j * w * Ca1 + 1/ Z4 ); Z6 = Rd + Z5 ; Z7 = 1 / ( j * w * C2 + 1/ Z6 ); Z8 = 1/( j * w * C1 ) + Z7 ; % currents i0 = u0 / ( Rs + Z8 ); % amplifier output id = i0 * Z7 / Z6 ; % damping resistor i1 = id * Z5 / Z4 ; % reader antenna coil i2 = i1 * j * w * M / Z2 ; % transponder antenna coil ic = i2 * Z1 / Rt ; % transponder chip % voltages ud = id * Rd ; % damping resistor uc = ic * Rt ; % transponder chip

Listing 3.1: Numerical system evaluation

35

t

If the calculations from listing 3.1 are performed for various frequencies, the frequency response of the system can be calculated. Since the system mainly consists of two resonators, it is useful to divide the system’s frequency response into two intermediate frequency responses, one for the reader and one for the transponder. As an interface between these two, the current i1 in the coil of the reader antenna is chosen, because it is proportional to the magnetic field strength which makes up the air interface. The definition of the two frequency responses can be found below.

|i1 | |u0 | |uc | |HT (jω)| = |i1 |

|HR (jω)| =

arg {HR (jω)} = arg {i1 } − arg {u0 }

(3.3)

arg {HT (jω)} = arg {uc } − arg {i1 }

(3.4)

3.1.4. Resonator Parameters From the frequency responses the resonator parameters Q, ω0 and gn can be extracted and the system can be approximated by two second order transfer functions like in equation group 3.5. In the following the process of parameter extraction will be described.

HR (s) = gR

1+

s ωR 1 s QR ωR

+

HT (s) = gT

s2 2 ωR

Reader Frequency Response

1+

s ωT 1 s QT ωT

+

(3.5)

s2 2 ωT

Transponder Frequency Response

35 10

Q = 31.9717 f0 = 13.5538 MHz

30

8 |HT| / gT

|HR| / gR

25 20 15

6 4

10 5 10

Q = 10.2092 f0 = 16.0041 MHz

2 12

14 16 f [MHz]

18

20

10

(a) Reader

12

14 16 f [MHz]

18

20

(b) Transponder

Figure 3.4.: Extraction of resonator parameters from frequency responses

36

Parameter Extraction First the resonance frequency f0 is determined by finding the peak of the amplitude response. After this the bandwidth B is found as the frequency span where the amplitude √ is reduced by a factor of 1/ 2. The quality factor Q is then calculated as f0 /B. At last the normalized gain factor gn is calculated as the maximum of the amplitude response divided by Q. Comparison of Frequency Responses Since the equivalent circuit contains 6 distinct energy storing elements, a transfer function that exactly describes this circuit will also be of 6th order at least. In fact the transfer function from the source voltage of the reader to the chip voltage of the transponder will be of even higher order. With the method of parameter extraction from numerically calculated frequency responses this high order transfer function is approximated by the product of two 2nd order transfer functions resulting in a 4th order model. A comparison of the numerical calculation and the 4th order model can be found in figure 3.5.

System Magnitude

System Magnitude 0.4

Numerical Calculation 4th Order Model

|HS|

|HS|

0.4

0.2

0 10

12

14

16

18

Numerical Calculation 4th Order Model 0.2

0 10

20

12

14

f [MHz] System Phase

20

200 arg(HS) [deg]

arg(HS) [deg]

18

System Phase

200 Numerical Calculation 4th Order Model 0

-200 10

16 f [MHz]

12

14

16

18

Numerical Calculation 4th Order Model 0

-200 10

20

f [MHz]

12

14

16

18

20

f [MHz]

(a) Distance of 15 cm

(b) Distance of 10 cm

Figure 3.5.: Comparison of system frequency responses From the diagrams above it can be seen that the system can be well described by a 4th order model. The system frequency response of figure 3.5a shows two peaks in magnitude. One is caused by the reader resonator which has a resonance frequency of 13.56 MHz and the other one is caused by the transponder resonator which is tuned to 16 MHz. However, the peak of the transponder resonator is only visible because of the large distance of 15 cm. At closer distances the limiter operation starts which reduces the transponder quality factor in a way that it is not visible in the frequency response any more. This can be seen in figure 3.5b where the system frequency response was simulated for a distance of 10 cm.

37

3.1.5. Baseband Representation With the method described above the channel transfer function in passband can be obtained. For signal processing it is, however, easier to work in baseband. Especially if the downmixing is done in the analog domain, a baseband representation of the channel is needed. In the following it will be shown how a second order transfer function in passband can be approximated by a first order transfer function in baseband [18] [19]. The resonator’s passband transfer function HPB , as it is shown in equation group 3.6 is taken as a starting point for the transformation.

HPB (s) = g

s s2 − 2σs + ω02

HPB (jω) = g

jω ω02 − ω 2 − j2σω

(3.6)

In the first step the denominator of HPB is approximated by a Taylor series expansion around the carrier frequency ωc that is aborted after the second term.

f (ω) = ω02 − ω 2 − j2σω

(3.7)

0

f (ω) = −2ω − j2σ

(3.8) 0

fapprox (ω) = f (ωc ) + (ω − ωc )f (ωc )

HPB_approx (jω) = g

jω ω02 − ωc2 − j2σωc + (ω − ωc )(−2ωc − j2σ)

(3.9)

(3.10)

Now it is shifted to baseband by the substitution ω 0 = ω − ωc or equivalently ω = ω 0 + ωc . This results in the baseband transfer function HBB .

HBB (jω 0 ) = g

j(ω 0 + ωc ) ω02 − ωc2 − j2σωc + ω 0 (−2ωc − j2σ)

(3.11)

With further modification this formula is brought into the following form. The right part of this equation is set up as a transfer function with one complex pole, located at pBB = σBB + jωBB and will be used for a comparison of coefficients.

HBB (jω 0 ) =

g 1 1 = gBB 0 2 −ω 2 −2ω 0 ω ω c 2 −σ − j 0 c jω − σBB − jωBB 2(ω 0 +ω

c)

38

(3.12)

From equation 3.12 it can be seen that gBB = g/2 and σBB = σ. To find the imaginary part of the pole’s location the following equation must be solved.



ω02 − ωc2 − 2ω 0 ωc = ω 0 − ωBB 2(ω 0 + ωc )



ωBB =

ω02 − ωc2 + 2ω 02 2(ω 0 + ωc )

(3.13)

For a frequency range that is smaller than the carrier frequency (ω 0  ωc ) the formula for ωBB can be approximated as follows.

ωBB ≈

ω02 − ωc2 ≈ ω0 − ωc 2ωc

(3.14)

The resulting baseband transfer function is summarized in equation 3.15. It can be seen that for ω0 = ωc the imaginary part of the pole’s location dissolves.

HBB (s) =

gBB s − (σBB + jωBB )

      

g 2 =σ

gBB = σBB

(3.15)

ωBB = ω0 − ωc

Interpretation of the Result The implementation of an analog filter is only possible if the coefficients of the underlying transfer function are real. A digital filter, however, can also be implemented with complex coefficients. It performs the convolution of a complex input signal with a complex impulse response which leads to a complex output signal. The impulse response of the baseband transfer function from equation 3.15 can be obtained by an inverse Laplace transform of the transfer function. The result is shown in equation 3.16.

hBB (t) = unitstep(t) gBB eσBB t ejωBB t

(3.16)

Because of the transformation to baseband, the input signal of this channel model is not the real valued passband signal, but it is the complex valued baseband signal. This baseband signal is obtained by IQ demodulation of the passband signal and consists of two components, the in-phase part I and the quadrature-phase part Q. These two parts can be combined as I +jQ which results in a complex signal that describes the amplitude and phase of the carrier in the complex domain. A block diagram of an IQ-demodulator and a visualization of the channel models in passband and baseband can be found in figure 3.6 on page 40.

39

(b) Passband

(c) Baseband

(a) IQ demodulator

Figure 3.6.: IQ demodulator and channel models in passband and baseband For the baseband channel model in figure 3.6c, a convolution of two complex signals has to be performed. For this purpose a complex multiplier is needed that operates according to equation 3.17. It can be seen that for a real impulse response (hBBi = 0), as it is the case by a perfectly tuned resonator, the effect on I and Q is the same. (I + jQ)(hBBr + jhBBi ) = (IhBBr − QhBBi ) + j(IhBBi + QhBBr )

(3.17)

Use of Channel Model for Equalization With the channel model presented above, a simple zero forcing equalizer can be implemented. The idea behind the zero forcing approach is to filter the received signal with a transfer function that is an inverse version of the channel transfer function. This way the distorting effects of the channel can be compensated. The disadvantage of this approach is that it also leads to an enhancement of noise, especially at higher frequencies. A possible implementation of a zero forcing transfer function is shown in equation 3.18. The pole of the baseband channel model is now transformed to a zero zBB . Additionally to this two poles have been added. The pole at pPS is used for pulse shaping and the pole at pLP is used to implement the lowpass filter needed by the IQ demodulator.

HZF (s) =

s − zBB (s − pPS )(s − pLP )

(3.18)

A more detailed evaluation of equalizer structures is beyond the scope of this work. In a closer examination it will have to be decided if the simple zero forcing approach presented above leads to satisfying results or if more elaborate techniques have to be applied.

40

3.2. Numerical Evaluation For the calculation of system parameters and evaluation of its dependencies a Matlab simulation script was written. A description of this script can be found in appendix A. In the following the results that were obtained by this script will be presented.

3.2.1. Circuit Quantities With the Matlab simulation script it is possible to calculate the system operation point for a specific setup. Exemplary values for this can be found in table 3.1a. The derived operation point was then used in an OrCAD simulation for verification of the circuit quantities obtained from Matlab. A comparison of results is shown in table 3.1b.

Setup 37.5 mm 7.5 A/m 10 Ω 16 MHz 5V

d Href 1 Rs ft uc

k

Matlab 0.0605

u0

19.16 V

Ct Rt

37.15 pF 87.24 Ω

Matlab 312.3 mA 2.102 A 60.18 mA 1.805 V 5.000 V

i0 i1 i2 ud uc

(a) Operation Point

OrCAD 313.9 mA 2.104 A 60.25 mA 1.807 V 5.006 V

(b) Circuit Quantities

Table 3.1.: Operation point and circuit quantities

K K1 K_Linear COUPLING = 0.060503 L1 = La1 L2 = La2

Rs

C1

Rd

Ra1

10

42.7pF

0.94

0.274

I

u0 19.16V

i0

I

C2 222pF

id

I

Ra2 1.286

i1

1

2 La1 477nH

Ca1 25.1pF

2

I

La2 2298nH

i2

V

Ca2 5.9pF

Ct 37.15pF

uc

Rt 87.24

1

0

0

Figure 3.7.: OrCAD simulation for verification of Matlab results

1

The field strength Href refers to a distance of 37.5 mm, which is the position of the calibration coil in the test setup of ISO 10373-6. In the following all field strength values will be specified as Href .

41

3.2.2. Reader Antenna The functionality of the impedance matching network has been verified by a simulation of the input impedance over a frequency range as it can be seen in figure 3.8a. At the operation frequency of 13.56 MHz it has a magnitude of 50 Ω and an angle of 0◦ . At other frequencies the magnitude and phase are different, therefore the matching is only valid for one frequency. In figure 3.8b the resonance frequency and the quality factor of the reader resonator are depicted as a function of the amplifier source resistance. The resonance frequency is tuned to 13.56 MHz with only little deviation. But the quality factor strongly depends on the amplifier source resistance. Because of the matching to 50 Ω, the quality factor drops by a factor of 1/2 if the amplifier source resistance is also 50 Ω. The conclusion of this fact is that the parameter quality factor has to be referred to a complete reader, not only to an antenna. Magnitude of Input Impedance

Resonance Frequency

f0 [MHz]

1.5 1 0.5 0 12

∠ Zin [deg]

13.58

12.5

13

13.5 14 14.5 f [MHz] Phase of Input Impedance

13.56 13.54 13.52 0

15

90

40

45

35

0

30

Q

|Zin| [kΩ]

2

10 15 20 25 30 35 40 45 50 Rs [Ω] Quality Factor

5

10 15 20 25 30 35 40 45 50 Rs [Ω]

25

-45 -90 12

5

12.5

13

13.5 f [MHz]

14

14.5

20 0

15

(a) Input impedance

(b) Resonator parameters

Figure 3.8.: Reader matching and resonator parameters for Q35 antenna

For the ISO antenna from page 29 two matching networks named Q35 and Q6 have been designed. Their component values and characteristic parameters can be found in table 3.2. For further simulations the Q35 network is used and Rs = 10 Ω is assumed.

Q35 Q6

Rd 0.94 Ω 6.6 Ω

C1 42.7 pF 106.5 pF

C2 222.2 pF 169.1 pF

Zin 49.999 Ω 49.999 Ω

QRs =0 Ω 38.31 6.86

QRs =10 Ω 31.8 5.65

Table 3.2.: Component values for antenna matching

42

f0 13.53 MHz 13.29 MHz

3.2.3. Transponder Operation The state of the transponder at various distances can be determined through the operation point calculation. Figure 3.9 shows a distance sweep from 0 - 20 cm for various field strengths Href . The maximum quality factor of 10 (right axis of 3.9b) results from the constant current of 2 mA that is assumed before the limiter gets active. Limiter Operation 2 A/m 4 A/m 6 A/m

5

Rt [kΩ]

uc [V]

4 3 2 1 0 0

2 A/m 4 A/m 6 A/m

3

12

2.5

10

2

8

1.5

6

1

4 2 A/m 4 A/m 2 6 A/m 0 15 20

0.5

5

10 d [cm]

15

0 0

20

(a) Chip voltage

5

10 d [cm]

Qt

Chip Voltage 6

(b) Limiter operation

Figure 3.9.: Transponder operation (uc = 5 V, ic = 2 mA, ft = 16 MHz)

3.2.4. Energy Range The energy range is defined as the distance at which the chip voltage reaches a level that is needed for operation. It is not only dependent on the field strength, but also on the transponder resonance frequency, as can be seen in figure 3.10. However, the actual system operation range defined by load modulation can be smaller. Energy Range

Energy Range

25

15 10 5 0 0

2 A/m 4 A/m 6 A/m

20 Range [cm]

Range [cm]

20

25 16 MHz 14 15 MHz 16 MHz 14

15 10 5

2 H

ref

4 [A/m]

6

0 10

8

12 14 16 Transponder f [MHz] 0

(a) Field strength

(b) Resonance frequency

Figure 3.10.: Energy range of transponder (uc = 5 V, ic = 2 mA)

43

18

3.2.5. Detuning Effects The term detuning denotes a deviation of the desired resonance frequency of a resonator. Such a deviation can be caused by a static error like a wrong set trim capacitor but it can also be caused dynamically during system operation as a result of the coupling between reader and transponder. Since the resonance frequency and also the quality factor of the reader resonator are essential channel parameters, it is important to examine the change of these parameters. Figure 3.11 contains the result of a distance sweep simulation that shows the change of quality factor and resonance frequency for both reader and transponder.

Quality Factor

Quality Factor

30

10 Q

15

Q

35

2 A/m 4 A/m 6 A/m

25 20 0

5

10 d [cm]

15

0 0

20

Resonance Frequency

10 d [cm]

15

20

16.15 2 A/m 4 A/m 6 A/m

f0 [MHz]

f0 [MHz]

5

Resonance Frequency

13.6

13.55

13.5 0

2 A/m 4 A/m 6 A/m

5

5

10 d [cm]

15

16.05 16 0

20

(a) Reader

2 A/m 4 A/m 6 A/m

16.1

5

10 d [cm]

15

20

(b) Transponder

Figure 3.11.: Detuning (uc = 5 V, ic = 2 mA, ft = 16 MHz) In figure 3.11a it can be seen that the reader quality factor decreases while its resonance frequency increases. The increase of resonance frequency is only caused by the operation of the limiter on the transponder. If the limiter functionality is not active, also the resonance frequency decreases as can be seen in the case of 2 A/m. The quality factor and resonance frequency of the transponder only depend on the operation of the limiter. If it is disabled, these parameters stay the same for all distances. This however is only the case for one transponder in the field. If there are multiple transponders they influence each other and change their resonance frequencies. An explanation for this will be presented on the next page.

44

Cause of Detuning Dynamic detuning between reader and transponder is caused by the induced voltage that results from the flow of current in the other coil. If there is a reader R and only one transponder T1, there is one induced voltage at the reader and one induced voltage at the transponder. The induced voltage at the reader is directed against the flow of current in the reader coil and can be interpreted as a transformed impedance. But the induced voltage at the transponder is the only voltage that is present in this circuit. Because of this it can not be interpreted as a transformed impedance, moreover it is the source voltage of this resonator. There will be detuning of the reader resonator but not of the transponder resonator. 0

1

0

1

10 1

01 0

Figure 3.12.: Detuning with one transponder If there are two transponder T1 and T2, the situation is different. In this case there is still the induced voltage from the reader, but there is also an induced voltage from the other transponder. The later one is directed against the source voltage and can therefore be interpreted as a transformed impedance. In this case there will be detuning of the reader resonator and also detuning of the two transponder resonators.

i0

i1

L0 R

i2

L1

jωM10*i1

jωM01*i0

jωM20*i2

jωM21*i2

L2 T1

jωM02*i0 jωM12*i1

Figure 3.13.: Detuning with two transponder

45

T2

3.2.6. Transformed Impedance A good way to predict the influence of the transponder on the reader is to calculate its effect on the transformed impedance. It can be visualized by a Nyquist plot where the impedance is plotted in the complex plain as a function of a system parameter. Distance Sweep

Load Resistance Sweep

0.1

0.05 2 A/m 4 A/m 6 A/m

20 cm 13.8 cm

2.5 kΩ -0.05 Imag{Zt} [Ω]

Imag{Zt} [Ω]

0

-0.1

-0.2



-0.1 -0.15



263.5 Ω

2.5 kΩ

178.3 Ω

-0.2

2.5 kΩ

-0.25

-0.3



131.2 Ω

-0.3 1 cm

1 cm 1 cm -0.4 -0.1

2 cm 4 cm 6 cm

0

0

0.1

0.2 0.3 Real{Zt} [Ω]

0.4

0.5

-1

(a) Distance

0

1 2 Real{Zt} [Ω]

3

4

(b) Load resistance

Figure 3.14.: Transformed impedance (uc = 5 V, ic = 2 mA, ft = 13.56 MHz) In figure 3.15a a distance variation between 1 cm and 20 cm is shown. At the largest distance the influence of the transponder on the reader is low and the transformed impedance has a value near 0 Ω. If the transponder approaches the reader, the real part of the transformed impedance rises and the imaginary part becomes capacitive. This behavior is consistent with the detuning effect that was presented in the previous section. In figure 3.15b the effect of a change in transponder load resistance is shown. The state of 0 Ω represents a closed load modulation switch and the state of 2.5 kΩ represents the state of idle operation while the limiter is not active. In between these two states there is the actual operation point of the limiter, marked with a diamond. This operation point was calculated for a field strength of Href = 4 A/m. From the diagram it can be seen that a reduction of transponder load resistance is sensed as a decrease of the transformed impedance’s real part while the imaginary part becomes slightly more capacitive. Influence of Transponder Resonance Frequency The simulations in figure 3.14 were carried out with a transponder resonance frequency of 13.56 MHz. This is however not realistic since the transponder resonance frequency has a large tolerance and will be somewhere between 13.56 MHz and 16 MHz. For a better understanding of the dependencies the behavior of the transformed impedance with other transponder resonance frequencies will be examined in the following.

46

Higher Resonance Frequency With a higher resonance frequency of ft = 16 MHz the limiter operation starts at a closer distance and before it starts the effect is increasingly inductive. This results in a decrease of reader resonance frequency while the limiter is not active. The load resistance sweep now shows a curve where the real part of the transformed impedance first increases and then decreases while the imaginary part constantly decreases. Distance Sweep

Load Resistance Sweep

0.2

0.8 2 A/m 4 A/m 6 A/m

10.8 cm

0 20 cm

1 cm

-0.2

0.4 0.2 0 -0.2

1 cm -0.4 -0.1

0

0.1

2.5 kΩ 2.5 kΩ 283.6 Ω

0Ω 0Ω

183.9 Ω 133 Ω



1 cm 0.2 0.3 Real{Zt} [Ω]

0.4

-0.4 -0.1

0.5

2 cm 4 cm 6 cm

2.5 kΩ

0.6

Imag{Zt} [Ω]

Imag{Zt} [Ω]

7.2 cm

0

0.1

(a) Distance

0.2 0.3 Real{Zt} [Ω]

0.4

0.5

(b) Load resistance

Figure 3.15.: Transformed impedance (uc = 5 V, ic = 2 mA, ft = 16 MHz) Lower Resonance Frequency With a lower resonance frequency of ft = 11 MHz the transformed impedance shows a similar behavior but with an inversion of the reactive effect. The distance sweep shows an increasingly capacitive effect before the limiter gets active and the load resistance sweep is now directed to an increase of the reactive part. Distance Sweep

Load Resistance Sweep

0.1

0.1 20 cm

2 A/m 4 A/m 6 A/m

0

-0.1 -0.2

-0.2 -0.3

0

4.5 cm

1 cm

Imag{Zt} [Ω]

Imag{Zt} [Ω]

9.9 cm -0.1 7.9 cm

1 cm

-0.4 -0.5

-0.3 -0.4

0Ω 0Ω 2.5 kΩ 0Ω

2 cm 4 cm 6 cm

354.6 Ω 199.6 Ω 139.5 Ω

2.5 kΩ

-0.5 -0.6

-0.6

1 cm

-0.7

-0.7

-0.8

-0.8 -0.1

-0.9 -0.1

0

0.1

0.2 0.3 Real{Zt} [Ω]

0.4

0.5

(a) Distance

2.5 kΩ 0

0.1 0.2 Real{Zt} [Ω]

0.3

0.4

(b) Load resistance

Figure 3.16.: Transformed impedance (uc = 5 V, ic = 2 mA, ft = 11 MHz)

47

3.2.7. Load Modulation The switching of the load modulation switch on the transponder is sensed at the reader as a variation of amplitude and phase of the received voltage that is measured across the damping resistor. How exactly this voltage is changed is depicted in figure 3.17.

1.2 1 0.8 0.6 0.4 0.2 0

Amplitude 1.4

2 cm 4 cm 6 cm

|ud| [V]

|ud| [V]

Amplitude

2 cm 4 cm 6 cm

1.2 1 0.8

0.5

1

1.5 Rt [kΩ]

2

0.6 0

2.5

0.5

1

Phase

2.5

20 2 cm 4 cm 6 cm

10 5

∠ ud [deg]

∠ ud [deg]

2

Phase

15

0 -5 -10 0

1.5 Rt [kΩ]

0.5

1

1.5 Rt [kΩ]

2

0 -10 -20 -30 0

2.5

(a) ft = 13.56 MHz

2 cm 4 cm 6 cm

10

0.5

1

1.5 Rt [kΩ]

2

2.5

(b) ft = 16 MHz

Figure 3.17.: Effect of load modulation on received voltage (Href = 4 A/m) If the transponder is exactly tuned to 13.56 MHz (figure 3.17a) a decrease of transponder resistance results in an increase of received voltage while its phase shows no big variation. With a transponder resonance frequency of 16 MHz (figure 3.17b), the amplitude first slightly decreases and then increases while the phase shows a constant increase. An important fact concerning these diagrams is that the effectively usable part for load modulation is limited by the limiter operation point which is marked with a diamond. The closing of the load modulation switch can only result in a decrease of transponder resistance from that point on. Therefore the overall effect of load modulation will be very little and the receiver must have a high sensitivity. For the design of a receiver the received voltage can be plotted directly in the IQ domain resulting in a constellation diagram. Such a diagram can be obtained from the data in figure 3.17 if the received voltage between transponder operation point and zero resistance is normalized to the unmodulated state and plotted in the complex domain. The constellation diagrams for the two cases presented above are depicted in figure 3.18 on the next page.

48

Constellation Diagram From the constellation diagrams below it can be seen that the closing of the load modulation switch mainly results in an increase of amplitude at the receiver. Constellation Diagram

Constellation Diagram

0.2

0.2 2 cm 4 cm 6 cm

0.15

2 cm 4 cm 6 cm

0.15

0.1

0.1

0.05

0.05 open Q

Q

open 0

0 -0.05

-0.05

closed

closed -0.1

-0.1

-0.15

-0.15

-0.2 0.8

0.9

1 I

1.1

-0.2 0.8

1.2

0.9

(a) ft = 13.56 MHz

1 I

1.1

1.2

(b) ft = 16 MHz

Figure 3.18.: Constellation diagrams of load modulation (Href = 4 A/m) Transient Behavior One important fact when it comes to Very High Data Rates is that the symbols presented in figure 3.18 will not be reached completely because of intersymbol interference. In figure 3.19 the transient behavior for different subcarrier frequencies is shown. These plots were obtained by filtering a rectangular wave with the baseband equivalent reader transfer function, derived in section 3.1.5. It can be seen that at 106 kHz the steady state and therefore the symbol is reached, whereas at 848 kHz it is not reached any more. Baseband Signal 106kHz

Baseband Signal 848kHz 1 Normalized Amplitude

Normalized Amplitude

1 0.8 0.6 0.4 0.2 0 0

0.8 0.6 0.4 0.2 0

5

10 t [μs]

15

20

0

(a) 106 kHz, QR = 35

5

10 t [μs]

15

(b) 848 kHz, QR = 35

Figure 3.19.: Transient behavior of baseband signal

49

20

3.3. Conclusion As a conclusion of this chapter the proposed channel models for up and downlink will be reviewed and first considerations on digital signal processing will be made.

3.3.1. Uplink The uplink channel can be well described by the product of two second order transfer functions which account for the reader and the transponder resonator. The dominating part is the reader resonator, since the quality factor of the transponder is lowered by the limiter according to the operation point. If a phase modulation is applied the signal will become distorted by the channel. Especially at phase changes of 180 ◦ the system has a long settling time which leads to intersymbol interference. To compensate this effect equalizer concepts can be applied. A good approach is to pre-equalize the symbols before they are sent from the reader. This adds no complexity to the transponder and compensates the channel. But since this compensation will not be perfect also an equalizer on the transponder side will most likely be needed. Furthermore the variation of the channel caused by detuning will most likely require adaptive implementations.

3.3.2. Downlink The downlink channel is inherently nonlinear. This results from the concept of load modulation where not a signal is modulated but the channel itself. In fact it is the reader resonator transfer function that is changed by the transponder. This change has an effect on the current in the reader coil and can be sensed as a variation of the voltage across the damping resistor. If the transient behavior of the modulation should be described exactly, a state space representation of the system is needed where the load modulation can be modeled as a variation of the channel parameters. However an easier approach is to linearize the channel and describe it only by the reader resonator transfer function. With the baseband equivalent of this transfer function a zero forcing equalizer can be designed that equalizes the I and Q part after the signal was downmixed to baseband. Because of channel variations also this equalizer will presumably have to be adaptive.

50

4. Conception of the Test Platform 4.1. Motivation For the development of Very High Data Rates a hardware setup is needed that allows measurements and validation of receiver concepts. In the following the motivation for the development of the Very High Data Rate Test Platform will be described.

4.1.1. Verification of Theoretical Results The results obtained by analytical and numerical calculations as they were presented in the previous chapter can be verified by results from other simulation software like OrCAD PSpice or Agilent ADS. If these results correspond to each other, it can be assumed that there is no flaw in the calculations. However, such a test cannot prove that the model that was used in the simulation sufficiently describes the real physical system. To prove this real physical measurements must be made. One of the main goals of the Test Platform is to provide the necessary hardware for these measurements. The following list contains an overview of important system characteristics. • Resonator parameters (f0 , Q) • Detuning of reader resonator • Effect of load modulation at various operation points • Distortion of phase modulated carrier by channel • Energy transfer to transponder

51

4.1.2. Validation of Transceiver Concepts Once models of the system and the channel have been constructed and verified, they can be used to design an adequate transmitter and receiver. In the first step the transmitter and receiver will be modeled in an abstract way. They can then be simulated along with the system model. The abstract receiver model can also be tested by real world data from measurements. If such simulations lead to satisfying results, a more realistic implementation of the receiver can be designed. For the design of digital signal processing structures a hardware description language like VHDL can be used. Such a design can then be synthesized for an FPGA and the receiver can be tested on real hardware. The Test Platform should provide the following possibilities. • Generation of various modulation schemes for up and downlink • Measurement of received signal for use in simulations • Implementation of transceiver concepts on real hardware • Validation and tuning of digital filter structures

4.1.3. Development of Test Methods The development of a new standard for Very High Data Rate systems requires also the development of test methods for these systems. In ISO 10373-6 [14] the test methods of the current standard ISO 14443 [3] are defined. These methods can be used as a basis for new test methods but will most likely have to be adapted or extended according to the new requirements. By the Test Platform the development of such new test methods should be facilitated.

4.2. Requirements From the desired functionality of the Test Platform and current system specifications requirements have been derived which will be presented in the following.

52

4.2.1. System Requirements The Test Platform will be subject of continuous development. Therefore both hardware and software have to be easily adaptable. A modular design should allow the extension or modification of the system if necessary. Signals within the system should be easily measurable with a digital sampling oscilloscope for further data processing.

4.2.2. Carrier Generation A central part of the Test Platform is a broadband, high frequency, power amplifier for the generation of the carrier signal. It is used in combination with the current test setup from ISO 10373-6 and should achieve field strengths of 1.5 - 7.5 A/m which are defined in this standard. The generated carrier signal should have a frequency of 13.56 MHz with a tolerance of ±7 kHz as it is defined in ISO 14443.

4.2.3. Data Transmission The Test Platform should provide the possibility to generate the modulation schemes which were presented in section 1.3.2. Therefore an analog phase modulated carrier signal has to be generated for the uplink and a digital control signal for the load modulation switch has to be generated for the downlink.

4.2.4. Receiver Concept The Test Platform should provide the possibility to implement receiver concepts fully digital on an FPGA development board. The only analog parts in the receive chain should be an anti-aliasing filter, a carrier suppression filter and a variable gain amplifier for level adjustment.

4.2.5. User Interface The FPGA development board should provide a simple user interface in form of push buttons and a liquid crystal display. Moreover it should be accessible over a serial interface which should allow the modification of filter coefficients or the setup of transmission data during operation.

53

4.3. Implementation The requirements that were stated above led to the block level design and selection of components that will be presented in the following.

4.3.1. Overview The system is divided into an FPGA board, a converter board, an amplifier board, a reader antenna including test fixture, and a transponder device. A block diagram of the system can be found in figure 4.1.

FPGA Board

VHD Converter

VHD Amplifier

Reader Antenna

ADC FPGA

OUT

DAC

IN

Air Interface Transponder MOD

Figure 4.1.: Block level diagram of VHD Test Platform The block diagram contains a transmission path that originates from the FPGA and goes over the DAC and the VHD amplifier to the reader antenna. The receive path originates from the reader antenna and goes over the VHD amplifier board and the ADC back to the FPGA. The VHD amplifier board contains therefore a part of the transmit path composed of lowpass filter and power amplifier and a part of the receive path composed of lowpass filter, carrier suppression, and level adjustment (not included in diagram). The setup as it is depicted in figure 4.1 is targeted for downlink measurements where an unmodulated carrier is generated by the amplifier and a digital load modulation signal is sent by the transponder. For uplink measurements a modulated carrier signal is generated by the amplifier and the receive signal can be obtained at the transponder. In this case the analog receive path must be connected to the transponder coil and the carrier suppression must be disabled.

54

4.3.2. FPGA As FPGA board the Xilinx ML506 was chosen which features the Virtex 5 FPGA with the designation XC5VSX50T. This FPGA contains 8160 Virtex 5 slices composed of four look up tables and four flip flops. It also contains 288 DSP48E slices, each with a 25 × 18 bit multiplier, an adder and an accumulator. The maximum amount of distributed RAM is 780 kB and the block RAM resources are 132 blocks of 36 kB. There is no PowerPC processor included like in the FXT series, but there is the possibility to build a softcore processor system with a Microblaze processor. The board contains a variety of peripheral hardware like an LCD, push buttons, an RS232 interface, 32 single ended digital IO pins and 16 pairs of differential digital IOs.

Figure 4.2.: Xilinx ML506 development board, including Virtex 5 SXT FPGA As system clock frequency eight times the carrier frequency namely 108.48 MHz is used. For this purpose a crystal oscillator1 from HKC with the designation X01050HD was chosen. This oscillator has a tolerance of ±50 ppm and comes in a DIL8 package which is compatible with the FPGA board.

4.3.3. Converters The converters operate at the system clock frequency of 108.48 MHz, have a resolution of 12 bit and are powered from the FPGA board. The ADC is a Texas Instruments ADS5520 and the DAC is an Analog Devices AD9752. These converters were chosen because they meet the requirements, are easily available and can be soldered manually.

1

It is important to use a crystal oscillator because programmable PLL-based oscillators exhibit too much jitter that interferes with the modulated data and can be a problem for carrier suppression.

55

4.3.4. Amplifier The amplifier has to generate field strengths of up to 7.5 A/m by use of the ISO 10373-6 test setup. For the design of the amplifier this requirement had to be converted to a requirement of output voltage. A Matlab simulation showed that the amplifier source voltage must be set to an amplitude of 19.187 V to reach this field strength, with the assumption of an amplifier source resistance of 10 Ω. The required maximum output voltage is therefore approximately 40 Vpp. This voltage is too high to be achieved by a single operational amplifier which is available up to a supply voltage of 24 VDC. Because of this the amplifier topology in figure 4.3 was conceived. G=4

G=1

1:1

G=1…2

4th Order

G=1…5

AD8056

AD8056

AD8056

THS3091

BD139/140

G=-4

G=1

THS3091

BD139/140

Figure 4.3.: Topology for broadband power amplifier At the input there is a variable gain preamplifier that allows the adjustment of the input voltage to a value of 1 Vpp. After that, there is an active 4th order lowpass filter. The cutoff frequency of this lowpass is set to two times the carrier frequency which is 27.12 MHz. This is enough bandwidth for the sending of phase modulated signals and leads to a good suppression of the quantization steps of the DAC, the first harmonics of which are at 108.48 MHz. After that, there is another variable gain preamplifier that allows the adjustment of the field strength between the limits of 1.5 - 7.5 A/m. All these parts are implemented with Analog Devices AD8056 operational amplifiers that need a supply voltage of 12 VDC. The circuitry that follows is supplied with 24 VDC. To reach the required 40 Vpp of output voltage, two complementary paths are designed that are finally combined by a transformer. First the voltage is amplified with Texas Instruments THS3091 operational amplifiers. After that, there are class AB amplifier stages composed of BD139 and BD140 bipolar transistors that are able to supply enough current to the output. At the end the two complementary signals are combined by a transformer to reach the double amplitude.

56

4.3.5. Receiver A block diagram of the analog receive path can be found in figure 4.4. It contains an anti-aliasing lowpass filter which is identical to the smoothing filter of the transmit path. It further contains a carrier suppression filter that can be used to suppress the frequency of 13.56 MHz by the use of a quartz crystal. Through a jumper it can be selected whether the lowpass and the carrier suppression, the lowpass only, or none of the filters should be used. At the end there are two variable gain amplifiers that should allow the amplification or reduction of the signal amplitude to meet the input range of the ADC. 1. CS + LP 2. only LP 3. no filter G=1

4th Order

Quartz Crystal

G=1…4

G = 0 … -4

Figure 4.4.: Topology for receiver circuit

4.3.6. Test Fixture The test fixture from ISO 10373-6 contains a reader antenna, two sense coils and a calibration coil which can be seen in figure 4.5 on page 58. The two sense coils are located at a distance of 37.5 mm above and below the reader antenna. They are connected to each other in a way such that the induced voltage of one sense coil has the opposite phase of the other one. If a transponder is added on top of the upper sense coil, the load modulation signal can be measured at the connection of the two sense coils, but the carrier is suppressed. On the lower side of the lower sense coil the calibration coil is mounted. The voltage which is induced in this coil can be measured by an oscilloscope and is proportional to the field strength. The amount of field strength at the calibration coil can be calculated by multiplying the induced voltage by the factor 1.1. The reader antenna in the middle of the fixture contains a group of five damping resistors and an impedance matching network, according to the topology presented in chapter 2.

57

Upper Sense Coil Reader Antenna Lower Sense Coil Calibration Coil

Figure 4.5.: Test fixture according to ISO 10373-6

4.3.7. Transponder For test purposes two transponder devices can be used. In compliance with ISO 14443 they are called proximity integrated circuit cards, abbreviated as PICC. The first one is the reference PICC like it is defined in ISO 10373-6. This is a simple model of a transponder, built with discrete components. It contains a rectifier, a variable damping resistor and a load modulation switch, implemented with a NAND gate. The second PICC is an evaluation board for an integrated analog transponder frontend in CMOS 090 technology. It contains a rectifier, a limiter circuit and an integrated load modulation switch. Pictures of the two PICCs can be found in figure 4.6.

(a) Reference PICC

(b) CMOS 090 PICC

Figure 4.6.: Transponder devices for use with VHD Test Platform

58

5. Analog Development 5.1. Transmit Path In the following the circuitry of the transmit path consisting of preamplifiers, lowpass filter and power amplifier will be described.

5.1.1. Preamplifier The two preamplifiers are depicted in figure 5.1. At the input of the first one the connection is terminated with 50 Ω to ground for matching of the coaxial cable. A coupling capacitor of 100 nF is used to block any DC current that could be caused by an offset of the input signal. The operation point of the amplifier is set to the middle of the supply range by a voltage divider. The amplifier itself is designed as a non inverting amplifier with one feedback resistor implemented as a potentiometer. The feedback is referenced to ground over a coupling capacitor, again to block DC current. The second preamplifier is built in the same way as the first one, but having a different voltage gain.

Figure 5.1.: Variable gain preamplifiers of transmit path

59

5.1.2. Lowpass Filter The 4th order lowpass filter is composed of a series of two 2nd order lowpass filters, implemented with a multifeedback topology as depicted in figure 5.2.

Figure 5.2.: 4th order lowpass with multifeedback topology The dimensioning of component values is aimed to reach a Butterworth lowpass transfer function. This characteristic was chosen because it has a flat amplitude response in passband. An ideal 4th order lowpass transfer function is depicted in equation 5.1. For a general description the complex variable s is normalized to the cutoff frequency ωc .

H(sn ) =

(1 + a1 sn +

A0 2 b1 sn ) (1

+ a2 sn +

b2 s2n )

with sn =

s ωc

(5.1)

The coefficients for the Butterworth lowpass can be found in data tables or they can be calculated by the following formulas: (for even order n)

ai = 2 cos

(2i − 1)π 2n

bi = 1

(5.2)

When the ideal coefficients are found, the circuit’s component values can be derived by a comparison of coefficients with the transfer function of the circuit’s topology. The transfer function for the multifeedback topology can be found in equation 5.3. The component designators in this formula refer to the bracketed designators in figure 5.2. Recommendations for the dimensioning of component values can be found in [20].

H(sn ) =

R2 /R1 1 + C1 (R2 + R3 + R2 R3 /R1 ) sn ωc + C1 C2 R2 R3 s2n ωc2

60

(5.3)

5.1.3. Voltage Amplifier The voltage amplification to a maximum amount of 20 Vpp is performed by a noninverting and an inverting operational amplifier circuit as depicted in figure 5.3.

(a) Non-inverting

(b) Inverting

Figure 5.3.: Voltage amplifiers with THS3091 The circuit topology is basically the same for both cases. The only difference between non-inverting and inverting is the point where the input signal is fed in. In both cases the operation point is set by a voltage divider at the positive amplifier input to the middle of the supply range. The feedback resistor network is dimensioned according to the recommendations in the data sheet of the operational amplifier. Because of standardized resistor values the voltage gain is not exactly the same at both circuits.

5.1.4. Current Amplifier After each voltage amplifier a class AB power amplifier stage was designed. Such a stage is depicted in figure 5.4 on page 62. It uses an npn (BD139) and a pnp (BD140) bipolar transistor that work together as complementary emitter followers. They are both conducting over more than 180 ◦ of the signal’s period to reduce crossover distortions. The necessary quiescent current for this operation is set by a bias voltage across the diodes. The output resistance of this stage is defined by the emitter resistors which is the reason why they are dimensioned very low.

61

Figure 5.4.: Class AB current amplifier stage

5.1.5. Transformer Output The two complementary signal paths are combined with the transformer depicted in figure 5.5. It is implemented with a ferrite core, wound with copper wire. Measurements showed that the used ferrite (FT140-61) has an AL 1 value of 330 nH. By the configuration of one loop each at the primary side and two loops on the secondary side, the input impedance of both sides at 13.56 MHz is + j112 Ω. By perfect coupling between the two sides the impedances would compensate each other and the transformer would add no inductive part to the output impedance. But since perfect coupling is not possible, in reality there will be some inductive part that is added to the output impedance.

Figure 5.5.: Transformer with balanced input, unbalanced output

1

The AL value is the inductance of one loop of wire. The inductance of N loops of wire can be calculated as L = N 2 AL .

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5.2. Receive Path In the following the receive path consisting of lowpass filter, carrier suppression and level adjustment will be described.

5.2.1. Lowpass Filter The lowpass filter in the receive path is the same as the lowpass filter in the transmit path which was presented in section 5.1.2 on page 60.

5.2.2. Carrier Suppression The carrier suppression is a bandstop filter with small bandwidth and high quality factor, a so-called notch filter. It is implemented with a quartz crystal that can be used for this because its equivalent circuit is a high quality factor resonator, as depicted in figure 5.6a. At resonance frequency it has a very low impedance, at other frequencies the impedance is high. Figure 5.6b shows the utilization of the quartz crystal in a filter circuit. It contains a voltage follower to stabilize the input and a voltage divider composed of a resistor and the quartz crystal. Additionally there is a potentiometer that can be used to increase the damping of the crystal if the bandwidth is too narrow.

(a) Quartz model

(b) Notch filter

Figure 5.6.: Quartz crystal used for carrier suppression

5.2.3. Level Adjustment The level adjustment at the end of the receive path is composed of two variable gain amplifiers that are comparable to the preamplifiers of the transmit path.

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5.3. Data Converters 5.3.1. Analog to Digital The ADS5520 is a 125 MSPS, 12 bit, CMOS integrated analog to digital converter, designed in a pipeline architecture. It needs a 3.3 V supply voltage and has a differential input range of 2.3 Vpp. In figure 5.7 the application circuitry of the ADC is shown.

Figure 5.7.: Circuitry for the analog to digital converter ADS5520 The chip has 12 data outputs (D00-D11), one synchronized clock output (CLKOUT) and one output that indicates an over range of the analog input signal (OVR). Because of the pipeline architecture the digital data will have a delay of 17 samples compared to the analog signal. The digital outputs should be equally loaded and need no external resistors in serial. The chip features a serial programming interface (SEN, SDATA, SCLK) which is not used and therefore connected to ground. The analog input (INP, INM) is differential and features an integrated switched capacitor sample and hold circuit. During operation each of the inputs must be biased to a common mode voltage that is supplied over the common mode pin (CM) of the chip. For the conversion of the single ended input signal to a differential signal a high frequency transformer is used. The common mode voltage is applied on the center tap of the transformer’s secondary winding. The termination of the input line to 50 Ω is also applied on the secondary winding. Additionally there are 25 Ω resistors in serial with the input pins to dampen potential ringing. The reference pins (REFP, REFM, IREF) are connected according to the recommendations in the data sheet. The reset pin (RESET) is connected to the FPGA which should apply a 2 µs long, positive reset pulse, 10 ms after the power supply has been switched on. The output enable pin (OE) is permanently set to high and the data format select pin (DFS) is permanently set to low, which selects straight binary data format and rising edge clock polarity for the digital outputs. The input clock for the chip is supplied by a single ended signal from the FPGA. The two differential clock pins (CLKP, CLKM) are internally biased to the common mode voltage CM.

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5.3.2. Digital to Analog The AD9752 is a 125 MSPS, 12 bit, digital to analog converter, designed in a segmented current source architecture. It operates with a 5 V analog supply and supports digital logic levels between 2.7 and 5 V. The application circuitry is depicted in figure 5.8.

Figure 5.8.: Circuitry for the digital to analog converter AD9752 The chip has 12 digital data inputs (DB00-DB11) that follow straight binary coding. The data is converted at the positive edge of the single ended clock signal (CLK). After a delay of 1 ns the converted data appears at the analog output with a settling time of 2.5 ns. At the digital signal pins a 22 Ω resistor is placed in serial to dampen potential ringing. The digital inputs are further terminated with external 50 Ω resistors (not depicted in schematic). The analog output is composed of two complementary current sources. The full scale current can be set between 2 and 20 mA. This allows a maximum voltage swing of 2 V at 50 Ω. The conversion to a single ended output signal is performed by a high frequency transformer, similar to the one at the ADC. The internal bandgap circuit is used as a reference voltage. This is set by connecting REFLO to ground. The 1.2 V reference voltage can be measured at the REFIO pin. The full scale current can be set over resistor R1 at the FS ADJ pin. The resulting value of the full scale current can be calculated as 32 × reference voltage/R1 . This results in a full scale current of 19.2 mA and an output voltage swing of 1.92 V at 50 Ω. If a load of the same value is connected to the output, the voltage will drop accordingly to the half value. The sleep mode is disabled permanently by a connection of the SLEEP pin to ground. The analog supply of the chip is connected to 5 V and the digital one to 3.3 V to support the same logic levels as the ADC.

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5.4. Final Result 5.4.1. VHD Amplifier Board The VHD amplifier board contains the analog transmit and receive path. A picture of the board can be seen in figure 5.9. Gain 1...4 Output OFF

Gain 0...4.5

Output ON

Gain 1...2

NO Lowpass

No Filter Lowpass Lowpass + Carrier Suppression

Connection of Primary Windings to Amplifier

Gain 1...5.5

WITH Lowpass

Intensity of Carrier Suppression

Trafo Output Single Amplifier Output

Figure 5.9.: VHD amplifier board including transmit and receive path The receive path is located at the upper side (input: right, output: left) and the transmit path is located at the lower side (input: left, output: right). For power supply there is a DC jack on the left that allows the connection of a 24 V adapter. Behind this connector there is a linear voltage regulator that can be identified by the black heat sink. Below are the operational amplifiers for the preamplifier and lowpass filter. The operational amplifiers for the voltage amplification are located at the bottom side of the board. On the right there are the four bipolar transistors with heat sinks that make up the power amplifier stage. Far right there is the transformer, composed of a ferrite ring with copper wires. The receive path on the upper side of the board has its own ground plane that is connected to the main ground near the power supply. The board features a number of jumpers and potentiometers which allow the setup of the desired mode of operation. A description of the possible adjustments can be found in the picture.

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5.4.2. VHD Converter Board The VHD converter board and its adapter for the connection to the FPGA board can be seen in figure 5.10. Adapter

Converter Board

RX IN (ADC)

TX OUT (ADC)

LOAD MOD

NEW PER

NEW SYM

LOAD MOD

Figure 5.10.: VHD converter board including ADC and DAC The converter board contains the ADC on the upper side and the DAC on the lower side. Right beside the chips there are the high frequency transformers. Additionally to the converters the board also contains connections for oscilloscope probes on the lower side. These connections can be used to measure digital signals. The wounded slices of wire serve as ground connections for the probes and should improve signal quality. The three digital signal connectors are named new period (NEW PER), new symbol (NEW SYM) and load modulation (LOAD MOD). The signal new period can be used to reconstruct the phase of the carrier. It toggles every time when the carrier undergoes a positive zero crossing. The signal new symbol is used for reconstruction of the data that was sent. It toggles every time when a new symbol begins. The signal load modulation is used to control the load modulation switch on the transponder. For this purpose it is also connected to an SMA connector on the right. The analog input (RX IN) and the analog output (TX OUT) are terminated with 50 Ω to ground. The full scale voltage of the ADC is 2.3 Vpp and the maximum output voltage of the DAC is 1.92 Vpp. However, it has to be considered that the voltages drop by a factor of 2, if the ports are connected to other ports that are also terminated to 50 Ω.

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5.4.3. Complete Test Platform A picture of the complete test platform in the setup for downlink measurements can be found in figure 5.11.

Figure 5.11.: Complete setup of test platform for downlink evaluation The setup consists of the FPGA board with attached converter board, the amplifier board and the test fixture including transponder. On the right there is an oscilloscope which is used to acquire signals for the evaluation of the downlink data transmission. On the display of the oscilloscope the signals NEW SYM, LOAD MOD and the receive signal can be seen. The depicted setup is a pure subcarrier with a frequency of 106 kHz.

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6. Digital Development The aim of the digital development is to create a data processing system on the FPGA that allows the transmission of the proposed modulation schemes from section 1.3.2 and the implementation and validation of possible receive structures.

6.1. Methodology In the following the methodological approach that was used for the digital development will be presented.

6.1.1. Design Approach For the selection of the desired modulation scheme and other adjustments, user interaction over the LCD and push buttons in form of a navigation menu will be needed. Such a menu could be implemented with a digital circuit, but this approach is complicated and the result is not easily adaptable. A more suitable solution is the implementation in software. This of course requires a microprocessor on which the software can be executed. With Xilinx Embedded Development Kit (EDK) a microprocessor system can be assembled, including user defined hardware blocks (IP1 cores) and the necessary software environment. For the Test Platform a Microblaze softcore processor system should be designed. The Microblaze processor is available as netlist and can be synthesized along with user defined hardware blocks for the FPGA. The user defined hardware blocks can be connected to the processor over the Open Peripheral Bus (OPB). As interface between the OPB and the hardware the standardized IP Interface (IPIF) is used. This allows the exchange of data through software accessible registers. The software that should run on the Microblaze processor can be written in C. Xilinx EDK also supports debugging facilities like a GNU software debugger or Xilinx Chipscope for hardware debugging.

1

Intellectual Property

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6.1.2. Hardware Description Language Because of the high symbol rates the generation of modulation schemes and possible receiver concepts have to be implemented in hardware. The hardware description language that should be used for this purpose is VHDL. The following design rules should apply. • Strictly synchronous design. All sequential units have a clk and a reset signal. Every action within these units is triggered only by a positive edge of signal clk. • In between units the following data types should be used: std_logic, std_logic_vector • In the design the following libraries should be used: std_logic_1164, std_logic_arith, std_logic_unsigned.

6.1.3. Simulation As simulation tool Mentor Graphics ModelSim 6.0 is used. The design files are added to a ModelSim project and are compiled into the library work. Xilinx EDK requires that the design files are part of a library that is named after the IP Core. Therefore a library mapping must be added to the ModelSim project that maps the design’s project library to the simulation library. The source code files are stored in a directory structure where every directory can contain a subdirectory and/or files with the ending *.vhd. For every source file name.vhd there should be a test bench called name_tb.vhd.

6.1.4. Synthetisation The synthetisation is performed by Xilinx EDK 9.1i, which utilizes the tools from Xilinx ISE. The development software provided by EDK is named Platform Studio. By Platform Studio a project can be created that contains the whole hardware and software design. If a completely new design should be created, the Base System Builder can be used to generate initial versions of all necessary design files. A central design file in Platform Studio is the Microprocessor Hardware Specification, which is a file with the extension *.mhs, located in the project directory. This file contains a list of all IP cores that compose the processor system, including its connections and characteristics. A visualization of this file is the System Assembly View in Platform Studio. Every change in its input mask will also modify the Microprocessor Hardware Specification. A screenshot of it can be found in figure 6.1 on page 71.

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Figure 6.1.: System Assembly View in Xilinx Platform Studio The user defined IP cores are stored in a directory outside the Platform Studio project directory that is called user repository. This user repository includes two subdirectories: drivers and pcores. In the folder drivers are the software files and in the folder pcores are the hardware files that compose a specific IP core. Within Platform Studio the Create or Import Peripheral Wizard can be used to generate template files that serve as a starting point for the development of user defined IP cores. This wizard creates subdirectories in the folders drivers and pcores that are named after the IP core, for example opb_vhd_testplatform_v1_00_a. This name is also the name of the library which the VHDL files should belong to. The VHDL files are then located in pcores/opb_vhd_testplatform_v1_00_a/hdl/vhdl. Initially there are the files opb_vhd_testplatform.vhd and user_logic.vhd. The first one contains an instantiation of the IP interface and of the user logic unit. The second one contains the user logic unit itself and can be used as a top level file for the development of user defined hardware. Beside these files there are also two other files that are important for the development of user defined IP cores. They are called Microprocessor Peripheral Description (MPD) and Peripheral Analyze Order (PAO) and can be found in the directory pcores/opb_vhd_testplatform_v1_00_a/data. The MPD file contains a list of all ports of the IP core. If user defined ports are added to the IP core, they must be entered in this file. The PAO file contains a list of all hardware source files which the IP core consists of. Therefore new files must be added in this list. If a user defined IP core is created in this way, it can be inserted in the System Assembly View in Platform Studio. To find the newly created IP core in the IP Catalog, the command Rescan User Repositories from the menu Project must be executed. After that, the IP core should be visible in the IP Catalog under Project Peripheral Repository and can be added to the System Assembly View. There the newly added IP core has to be connected to the OPB, external ports have to be connected to the outside and address

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ranges have to be generated. The mapping of external ports to pins of the FPGA must be entered in the User Constraints File which has the ending *.ucf and can be found in the project directory under the folder data. The complete processor system can be synthesized with the command Generate Netlist from the menu Hardware. This will create the bitstream file system.bit in the project directory under the folder implementation. This file contains the generated hardware and can be used to configure the FPGA. But it does not contain any software. The software can be added to the bitstream in form of initialization data for the Block RAM (BRAM). If a software project which is marked to initialize BRAM is compiled, it is added to the bitstream and stored in a separate file called download.bit. This file contains both hardware and software and can be downloaded to the FPGA. The download can be performed with the program Impact or directly from Platform Studio with the command Download Bitstream from the menu Device Configuration.

6.2. VHD IP Core The transmit and receive structures and an additional validation block are implemented as an IP core with the name opb_vhd_testplatform_v1_00_a. Figure 6.2 shows a block level diagram of the IP core’s structure.

Figure 6.2.: Overview of VHD IP Core

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6.2.1. User Logic Interface For the communication between the software application and the hardware of the IP core a number of software accessible registers are implemented. The definition of these registers can be found in table 6.1. (MSB: 0, LSB: 31) slv_reg1

slv_reg0

bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0-15

bit 0 - 31

purpose direction tx_en rx_en ber_en carrier_en subcarrier_en source_select sym_rate(0) sym_rate(1) sym_rate(2) subcarrier(0) subcarrier(1) subcarrier(2) bits_per_sym(0) bits_per_sym(1) bits_per_sym(2)

purpose memory_range slv_reg2

bit 0 - 31

purpose ber_length slv_reg3

bit 0 - 31

purpose received_symbols slv_reg4

bit 0 - 31

purpose received_bits slv_reg5

bit 0 - 31

not used

purpose not used

Table 6.1.: Software accessible registers of VHD IP core The main control register is slv_reg0. It controls the operational state of the units and defines the modulation scheme. The direction bit is used to discriminate between uplink and downlink. The bits tx_en, rx_en and ber_en are used to enable the functionality of the corresponding unit and the bits carrier_en and subcarrier_en are used to activate the generation of the carrier or subcarrier. With the source_select bit it can be decided whether the transmission data should be generated by a random generator or loaded from a memory. The signals sym_rate, subcarrier and bits_per_sym define the modulation scheme. The coding of modulation schemes is defined in table 6.2 on page 74. The value in slv_reg1 defines the number of bits that should be sent from the memory if this option is selected. In slv_reg2 the number of symbols for one bit error rate calculation is written by the software. During operation the values in slv_reg3 and slv_reg4 are incremented with every symbol or bit error that is detected. At the end an interrupt is generated and the bit error rate can be calculated by the software.

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sym_rate, subcarrier

value 000 001 010 011 100 101 110 111

fraction of fc fc /128 fc /64 fc /32 fc /16 fc /8 fc /4 fc /2 fc

bits_per_sym

frequency 105.94 kHz 211.88 kHz 423.75 kHz 847.50 kHz 1695 kHz 3390 kHz 6780 kHz 13560 kHz

value 000 001 010 011 100 101 110 111

bits 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit

PSK order 2-PSK 4-PSK 8-PSK 16-PSK 32-PSK 64-PSK 128-PSK 256-PSK

Table 6.2.: Signals for selection of the modulation scheme

6.2.2. Transmission Unit A block diagram of the transmission unit can be found in figure 6.3. All blocks are connected with the system clock and the global synchronous reset signal. memory interface slv_reg1

data_bit

data source

symbol

phase

symbol generation

symbol mapping

DAC_data

uplink

DAC_clk new_period new_symbol

bit_en load_mod

downlink

gen_en slv_reg0

mode control

map_en

symbol buffer

sym_en

tx_data

tx_sync

Figure 6.3.: Overview of transmission unit of VHD IP core

In the following the functionality and implementation of each block will be described. A simulation result of the complete system can be found in figure 6.4 on page 78.

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Mode Control Since every block in figure 6.3 is clocked at 108.48 MHz, enable signals are needed to control the timing. These enable signals are pulses of the duration of one clock period that come periodically according to the symbol rate. The generation of these signals happens in the mode control block. This block produces three enable signals: generation enable (gen_en), mapping enable (map_en) and symbol enable (sym_en). The first one triggers the generation of a new symbol, the second one triggers the mapping from a symbol to a phase value and the last one triggers the output of the symbol, in form of a phase value, over the uplink or downlink block. Because of the delay of one clock cycle between the enable pulse and the output of the result at the symbol generation and symbol mapping block, the enable signals are delayed to each other by one clock cycle. The described functionality is implemented with a counter that is clocked with the system clock frequency of 108.48 MHz. Depending on the selected symbol rate a specific bit of this counter is fed into a two bit shift register and an edge detection through the use of a XOR conjunction is applied to it. The result is a pulse signal of a duration of one clock cycle and a frequency that can be calculated as 108.48 MHz/(2 ∧ valence of counter bit). This means if the most significant bit of an 11 bit counter is fed into the shift register, the resulting pulse will come at a frequency of 105.94 kHz, which is the lowest symbol rate that should be generated. The delay in between the three enable signals is created with another shift register.

Data Source The generation of data bits is controlled by the signal bit_en. If this signal is high, the data source unit will output a single data bit on the rising edge of the clock signal. It can be selected if this data bit should be generated by a random generator or loaded from a software accessible memory. The random generator produces a pseudo random binary sequence (PRBS). It is implemented as a linear feedback shift register (LFSR) of a length of 20 bit and a tap specification of [20,17]g. Since this tap specification forms a maximum length LFSR, the generated bit sequence will exhibit no repetition for 220 − 1 bits. The software accessible memory has a size of 256 × 32 bit. It can be accessed through a read or write operation to a specific address range. Because of the characteristics of the user logic interface to the OPB, it is implemented as 4 blocks of 256 × 8 bit dual port block RAM with synchronous read. A description of recommended block RAM implementations can be found in the XST user guide [21].

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Symbol Generation The data bits from the data source unit are formed into symbols by the symbol generation unit. The maximum number of bits that are coded in one symbol is 8 which allows a maximum PSK order of 256. The signal symbol is therefore a vector of 8 bits. If a lower order PSK should be generated, which requires fewer bits in one symbol, only the lower bits of this vector are used. The number of bits that should be coded in one symbol is defined by the signal bits_per_sym, coded as in table 6.2. The implementation of this block is basically a shift register with serial load and parallel output. When the generation enable pulse is applied, the current value in the symbol register is output on the signal symbol at the rising edge of clk. At the same time the loading of the next symbol begins. For this purpose the signal bit_en is set to high and keeps this state for the next 1 - 8 clock cycles. How long it keeps high is defined by the signal bits_per_sym. At the highest symbol rate of 13.56 MHz, which has a symbol period of 8 clock cycles, and the highest order PSK, which requires 8 bits per symbol, the bit_en signal stays high for all the time. At this mode of operation the output of the current symbol is performed at the same time as the last bit is read in.

Symbol Mapping The symbol mapping block maps the symbol consisting of data bits to a phase value that can range from 0 - 360 ◦ . Because of the maximum PSK order of 256 this angle is scaled to a value between 0 - 255. The mapping of the data symbol to a phase value should lead to a distribution of the symbols in form of a gray code around the unit circle. Because of this a conversion from gray coded data to decimal coded data must be performed. For the implementation of this block a combinatorial circuit is used that converts binary reflected gray code to the decimal code. The circuit consists of XOR conjunctions and was taken from [22]. To prevent problems with combinatorial delay the circuit is implemented sequentially with a register that is filled bit by bit, with two bits at the first clock and one bit at every consecutive clock.

Uplink The uplink block generates data for the DAC that should represent the carrier signal. In the setup for the uplink the carrier can be phase modulated at a maximum of 256-PSK. Additionally this block generates the signals new_period and new_symbol, which toggle at the beginning of every new carrier period or symbol.

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The block is implemented with a 256 × 12 bit ROM that contains one sine period. This ROM is addressed by an 8 bit counter, which is incremented by a value of 32 every clock cycle. This way the whole table is traversed within 8 cycles. When the sending of a new symbol is triggered with symbol_en, the value stored in the signal phase is used as a reload value for this counter. If a PSK order of less than 256 should be generated, the phase value must be scaled to 255 which can be performed by a binary left shift.

Downlink The downlink block generates a square wave signal of a frequency defined by the signal subcarrier and a phase defined by the signal phase. If the sending of a new symbol is triggered by sym_en, the phase of this square wave is updated to a new value. The described functionality is implemented with a counter of variable module (value where an overflow occurs) and variable reload value. The period of one counter run is half the length of one subcarrier period. At the end of every counter run a signal called load_mod toggles its state. This way the unmodulated square wave can be generated. For the phase modulation the counter is loaded with a value defined by the signal phase. The most significant bit of this signal defines the initial state of load_mod and the other bits are used to reload the counter. If the phase value is all zeros, the generated load_mod signal will be zero for half the subcarrier period, followed by a state of one for half the subcarrier period. This is repeated periodically. If the reload value is higher than zero, the whole square wave is shifted to the left. Because of the variable bit width of the counter’s module and the signal phase the reload value needs to be scaled to the counter’s bit width.

Symbol Buffer The symbol buffer unit is used to temporarily store the signal symbol from the symbol generation block. When it is sent over the uplink or downlink, it is passed over to the output such that it can be used as a reference for an external bit error rate block. Along with the data also a synchronization pulse is generated that can be used to synchronize an external receiver block. The functionality is implemented as two 8 bit registers. If sym_en is high, the symbol is stored in the first register at the rising edge of clk. At the same time the content of this register is passed over to the second register, which is the output signal tx_data. The synchronization impulse tx_sync is generated as a registered version of sym_en. Therefore it is delayed by one clock cycle. If tx_sync is high, the sending of symbol tx_data over the uplink or downlink begins at the next rising edge of clk.

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Figure 6.4.: Simulation result of transmission unit for up and downlink

78

clk

0

200

3

2

400

2

3 0

0 3

2

600

2

2

3 0

800

0

0 3

Entity:tx_tb Architecture:bhv Date: Wed Jul 22 13:21:12 Westeuropäische Normalzeit 2009 Row: 1 Page: 1

tx_sync

tx_data 0

load_mod

new_symbol

new_periode

dac_data

bit_en

gen_en

map_en

sym_en

symbol 0

phase 0

tx_en

subcarrier_en

carrier_en

direction

reset

3

2 2

3 0

0

1 us

3

2 2

3

1200

1

2

1 0

0

0 1

1400

1

1 2

3

6.2.3. Receive and Bit Error Rate Unit The receive and the bit error rate unit are black boxes that were included as a basis for further development. The implementation of these units is beyond the scope of this work. The only features that have been implemented so far is the reading of data from the ADC and the generation of interrupts from the BER unit. For evaluation and debugging purposes a Chip Scope Integrated Logic Analyzer core was inserted that allows the readout of the ADC data and other signals over the JTAG interface.

6.3. LCD IP Core The implementation of a navigation menu consisting of push buttons and LCD requires additional IP cores that make up the interface between hardware and software. For the push buttons a GPIO2 IP core can be used that is included in Xilinx Platform Studio. For the access to the LCD a protocol must be implemented to communicate with the LCD controller. It would be possible to use a GPIO IP core as an interface to the hardware and implement this protocol in software. However, this is not the approach that was chosen, but it was decided that a user defined IP core should be created that implements this protocol in hardware.

6.3.1. LCD Hardware The LCD included on the ML506 development board is a Tianma TM162VBA6. The display has two lines of 16 characters each that are composed of 5×8 pixels. On the PCB of the LCD the controller chip KS0066U is included that generates the necessary signals to drive the individual pixels of the display. This chip features 16 common outputs and 40 segment outputs. With the extension driver KS0065B additional 40 segment outputs can be generated. This way the whole amount of pixels on the display can be addressed. The communication between the FPGA and the LCD controller happens over a protocol that is compliant with the HD44780 standard, which is the most common standard of LCD controllers. This protocol features communication over an 8 bit or a 4 bit bus. On the ML506 board only 4 bits of the data bus are connected. Therefore only 4 bit mode is possible. Additionally to the data bus there are three control signals: register select (RS), read/write select (RW) and enable (EN). A description of the protocol can be found in the data sheet of the LCD controller [23].

2

General Purpose Input Output

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6.3.2. User Logic Interface Since the display features two lines of 16 characters, a total of 32 characters can be displayed. The interface between IP core and software consists of 8 × 32 bit registers. This makes a total of 32 byte, where each byte represents a character on the display. If new data is written into the registers, the corresponding line on the display is updated.

6.3.3. State Machine The communication over the 4 bit protocol is implemented with a finite state machine. The corresponding state diagram can be found in figure 6.5. This state machine is enabled every 256th clock cycle and a state transition occurs with every second enable.

read

1

high_bits = ’0’ || low_bits = ’0’ read high or low bits

2

busy = ’1’

read busy flag

init = ’0’

instr

store instr in dout

1 2

Start 1

high_bits = ’0’ || low_bits = ’0’

update init counter 2

idle 5

transmit high or low bits

3

write_data = ’1’

4

store character in dout

rewrite_reg_line0 = ’1’ || rewrite_reg_line1 = ’1’

update char counter 2

data

store address in dout 1 high_bits = ’0’ || low_bits = ’0’

write_data
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