A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology

A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology S. Sankaran, S. Arai#, R. Augur^, M.Beck1, G. Biery, T. Bolom^, G. Bonilla, O. Bravo, K. Chanda, M. Chae1,F. Chen, L. Clevenger, S.Cohen, A. Cowley, P. Davis, J. Demarest, C. Dimitrakopoulos, L. Economikos, D. Edelstein, R. Filippi, J. Fitzsimmons, N. Fuller, S, Gates, S. Greco, A. Grill, S. Grunow, R. Hannon, K. Ida*, D. Jung, M. Kelling^, T. Ko, K. Kumar, C. Labelle^, H. Landis, M. Lane, W. Landers, M. Lee, W. Li, E. Liniger, X. Liu, J. Lloyd, W. Lu3, N. Lustig, K. Malone, S. Marokkey1, G. Matusiewicz, P. S. McLaughlin, P. V. McLaughlin, S. Mehta, I. Melville, K. Miyata*, B. Moon1, S. Nitta, D. Nguyen, L. Nicholson, D. Nielsen, P. Ong^, K. Patel, V. Patel, W. Park2, J. Pellerin^, S. Ponoth, K. Petrarca, D. Rath, D. Restaino, S. Rhee^, E. Ryan^, H. Shoba, A. Simon, E. Simonyi, T. Shaw, T. Spooner, T. Standaert, J. Sucharitaves, C. Tian, H. Wendt1, J. Werking^, J.Widodo3, L. Wiggins, and T. Ivers.

IBM Systems and Technology Group; ^Advanced Micro Devices, Inc.; *Sony Electronics, Inc.; #Toshiba America Electronic Components, Inc.; 1Infineon Technologies, A.G.; 2Samsung Electronics Co., Ltd.; 3Chartered Semiconductor Manufacturing Ltd; IBM Semiconductor Research and Development Center (SRDC), 2070 Rte. 52, Hopewell Junction, NY 12533 I. Abstract A high performance 45 nm BEOL technology with proven reliability is presented. This BEOL has hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impacts of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2x wiring levels, and increased 1x wire aspect ratios in low-k, both done without compromising reliability. This design point is found to maximize system performance without adding significant risk, cost or complexity. The new ULK SiCOH film was developed to have superior integration performance and mechanical properties at the expected k-value. The identical dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK Chip-Package Interaction (CPI) reliability, including in the most aggressive organic flip-chip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria. II. BEOL Integration and Reliability Aggressive 0.7x scaling from 65 nm BEOL wiring and contact dimensions has been achieved using hyper-NA lithography. This enables a 2x active area reduction for migratable designs. The 45 nm BEOL hierarchy is shown in Fig. 1. At the 1x wiring levels (M1-M3), BEOL delays are largely impacted by resistance increases from scaling. Increased aspect ratios in conjunction with an optimized Cu barrier-seed process result in up to 25% resistance and 20% RC reductions, respectively, per Fig. 2. Typically, increasing Cu aspect ratios degrades stressmigration (SM) and electromigration (EM) reliability. However, Fig’s. 3-4 show than an optimized Cu barrier-seed process and tooling enables zero SM fails and good EM performance. Thus scaling impacts to BEOL parasitics at 45 nm 1x levels are mitigated, while extending the low-k SiCOH film and integration scheme [1] from 90 and 65 nm technologies [2]. The industry-wide effort to integrate ULK BEOL dielectrics has focused primarily on the 1x wiring levels [3-5]. In contrast, our strategy is to introduce ULK at the 2x levels (M4-M6), which are typically dominated by relatively longer RCdominated runs. The 15% RC benefit for ULK (k=2.4) over low-k (k=3.0) at these levels, as shown in Fig. 5, is leveraged to deliver superior BEOL performance at reduced risk. These 2x levels consist of dual damascene Cu in homogeneous PECVD ULK porous-SiCOH which is based on advanced precursors and UV-cure tooling [7-8], resulting in a film with superior plasma damage and cracking resistances compared to commercially available films at similar k (and some SiCOH films at higher k). Some film properties are shown in Table 1. The UV cure does not cause any device damage, as shown in Fig. 6. As seen in Fig.

7, this ULK SiCOH enables direct CMP without detrimental effects to k. In contrast, most reported ULK integrations involve hybrid integration [4-5], pore-sealing methods [5], or at least CMP hardmasks [3-5]. The present ULK SiCOH enables identical non-poisoning dual damascene integration [1] as our prior CMOS generations, and as the other 45 nm wiring levels in lowk SiCOH. Overall, no fundamental changes were made to patterning or metallization schemes, comprised of sacrificial PVD TaN/Ta/Cu, optimized RIE with in-situ strip, conventional plating, direct eCMP, and no remnant ILD damage, per Fig. 8. Extensive BEOL reliability tests included EM, TDDB, SM, TC, and other screens. Fig’s 9, 10 and Table 2 show examples of ULK stress results on multiple lots/wafers; these all meet the same reliability criteria as dense dielectrics. Since introduction of porous ULK into the BEOL has been an industry-wide concern due to weak mechanical integrity during packaging, a comprehensive Chip-Package Interaction (CPI) reliability assessment was done. Special test chips with various failure monitors were packaged into flip-chip ceramic, flip-chip organic (Fig. 11), and organic wirebond packages as summarized in Table 3. Sonoscan images in Fig. 12 indicate that ULK fracture from packaging stresses can be eliminated by an optimized dicing methodology. These modules were processed through JEDEC level 3 preconditioning and stressed either at -55/+125C or -40/+125C for deep thermal cycle (DTC) and 85C/85RH/3.6V for temp/humidity/ bias (THB). DTC stress results are summarized in Table 4. In conjunction with optimized dicing, an advanced crackstop was developed which offers 5x the toughness in less than half the total footprint vs. the standard crackstop used for the Table 2 data. This should add CPI reliability redundancy, and improve ULK extendibility to more levels and lower dielectric constants. The relative toughness of the ULK SiCOH/Cu cap interface vs. the two crackstops are shown in Fig. 13. III. Conclusions A leading 45 nm CMOS BEOL technology featuring the first qualified implementation of porous ULK materials has been demonstrated. Results from integration, comprehensive reliability and Chip-Package interaction assessment has been presented. IV. Acknowledgments The authors would like to acknowledge the support of the E. Fishkill 300mm Fabrication facility. This work is supported by the independent alliance programs for SOI technology development and Bulk CMOS technology development. V. References [1] W. Cote, et al., Adv. Metalliz. Conf., 2006 (to be published). [2] D. Edelstein, et al., IITC, 214, 2004; M. Angyal, et al., Adv. Metalliz. Conf., 39, 2005. [3] Y. N. Su et al., IEDM, 91, 2005. [4] M. Tagami, et al., VLSI Tech, 2006. [5] Y.Kagawa, et al., IITC, 207, 2006. [6] S. Gates et al., submitted to Adv. Metalliz. Conf. 2006. [7] A. Grill, et al., Mat. Res. Soc. Symp. Proc., 612, 2001. [8] S. Gates et al., submitted to Adv. Metalliz. Conf. 2006.

Delta (%)

Resistance

1 Al

99.99 99

Electromigration 1x levels

1

3 4 Capacitance

2

Delta (%)

M9-M10 F-TEOS

P e r c e n tile

95 90

M7-M8 Low-k

75 50 25 10

M4-M6 ULK

5

M1-M3 Low-k

1

2

3

RC4

1

Delta (%)

Fig 1. Cross section of 10-level BEOL. 5

5

10

10

50

50

Time to Fail

100

500

100

1000

500 1000

Time to Fail AR=1.75

AR=2.0

AR=2.25

Fig 3: BEOL Electromigration performance on Cu/low-k wires at 1x levels.

AR=2.5

Fig. 2. Increase in aspect ratio at 1x thinwire levels can achieve RC improvements without changes to dielectric material. M2 Passive Resevoir 0.25um from Plate to Line 120 100 80 60 40 20 0 1900/3200

1900/3200

1900/3200

1500/3000

1500/3000

1500/3000

Material Properties of POR Porous low- k k @ 150oC

2.4

Stress, MPa

43

Modulus, GPa

4.6

Hardness, GPa

0.68

Breakdown field, MV/cm

> 7.5

Volume % porosity (EP)

25

%Fails

M2 Passive Resevoir 1.05 um from Plate to Line

120 100 80 60 40 20 0

T0 Yield T250 Fail%

V2 Chain, 4M Vias

T500 Fail%

120 100 80

1 9 0 0 /3 2 0 0

1 9 0 0 /3 2 0 0

Isolated V2 via

1 9 0 0 /3 2 0 0

100

1 5 0 0 /3 0 0 0

1 5 0 0 /3 0 0 0

120

1 5 0 0 /3 0 0 0

T750 Fail%

60 40 20 0

Table1: Properties of porous ULK SiCOH film.

80 60 40

E

F

1 9 0 0 /3 2 0 0

D

1 9 0 0 /3 2 0 0

C

1 9 0 0 /3 2 0 0

B

1 5 0 0 /3 0 0 0

1 5 0 0 /3 0 0 0

0

1 5 0 0 /3 0 0 0

20

Liner A

Fig. 4. Optimized liner/seed process results in good stress migration results on multiple structures at 1x levels with aggressive aspect ratios of ~2.5.

1.50

6.00

3.50 3.00 2.00

0.70 0.5

0.7

0.9

1.1

1.3

1.5

1.7

R/R0

Fig. 5. Measured R vs. C for 2x Cu wiring in k=2.4 ULK SiCOH and modeled data for k=3.0 SiCOH.

0

4

8

Fig. 6. No Vt shift observed on multiple de-

vices following UV cure.

IBM ULK

20 10

0.80

1.00

Measured data for k=2.4

Dense SiCOH

1.50

0.90

Commercially available ULK

2.50

After UV Cure

K=2.4

20

4.00

K=3.0

1.00

40

1.10

k - Value

4.50

∆ VTFS (mV)

1.20

Pre-CMP Post-CMP

K=2.3

5.00

Simulation for for k=3.0

1.30

C /C 0

5.50

Before UV Cure

40

1.40

12

Fig 7: New ULK SiCOH film enables direct CMP without detrimental effect to film or k value compared to commercial ULK SiCOH.

99

Normalized to 5MV/cm 99.99 99

Porous Low-k 100nm spacing

50

Electromigration 2x levels

95 90

Percentile

C u m m u la tiv e F a ilu re s (% )

90

10

75 50 25 10

Low-k 75nm spacing

5

5 1

5

1

1e1

Figure 8: Cross sectional SEM &TEM of Cu/ULK SiCOH dual damascene wiring.

Structure (Total 80 macros)

1e2

1e3 1e4 1e5 1e6 Stress Time to Fail (sec)

Thermal Cycle Fails @ -65 to 150ºC /1000 Cycles

100

500

10LM

8LM

10LM

8LM

1x Low-k Via Chains

0/68

0/68

0/204

0/204

1x Low-k Kelvin

0/68

0/68

0/204

0/204

2x ULK Via Chains

0/68

N/A

0/204

0/204

2x ULK Kelvin

0/68

N/A

0/204

0/204

M1-M7 Stacked Vias

0/68

N/A

1*/ 204

0/204

BEOL Si Fig. 11: Cross sectional SEM of FCPBGA chippackage reliability stressing module.

Table2: Stressmigration and Thermal Cycle data on 10-level BEOL stacks show no systematic failure modes. Test chip

No Delaminations observed after dicing optimization

Fig. 12. Sonoscan images of post-stress organic flip-chip modules. Chip delaminations induced by packaging stress (left), no delaminations (right) by optimized dicing. 11 10

# of metal layers

Chip size (mm)

Package

Flip chip

8 Cu + 1 Al

14.7 x 14.7

Multilayer ceramic Land grind array (MLC-LGA)

Wirebond

7 Cu + 1 Al

10 x 10

Macros designed-in

Perimeter lines, Intertwined via chain, Stacked vias, Delamination Flip chip plastic sensors, ball grid array Serpentines with (FCPBGA) various metal Enhanced width, special plastic ball grid Structures array (EPBGA) wirebond pads

Table 3: Summary of CPI test chips and corresponding packages.

Test chip

Packaging

Deep thermal cycle stress

Flip chip

MLC-LGA

0 fails after 1000 cycles of -55/+125C stress.

FCPBGA

0 fails after 1800 cycles of -40/+125C stress.

EPBGA

0 CPI fails after 1000 cycles of -55/+125C

9 8 7 6 5 4 3 2 1 0

Wirebond Interface

CS1

1000

C4

* Related to misprocess

R elativeToughness

50

Time to Fail

Fig. 9 TDDB (5 MV/cm stress) for Fig 10: Electromigration performance of Cu/ULK. 75nm wire spacing in low-k (k=3.0) vs. 100nm spacing in ULK (k=2.4).

Stressmigration Fails @ 175ºC /1000 Hours

Delaminations observed

10

1e7

CS2

Fig. 13: Relative toughness of the porous ULK/Cu cap interface, crackstop #1 for the data shown in Table 2, and crackstop #2 optimized for ULK.

Table 4: CPI results on flip-chip and wirebond packages.